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ds1877 sfp controller for dual rx interface _______________________________________________________________ maxim integrated products 1 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxims website at www.maxim-ic.com. 19-5188; rev 1; 4/10 general description the ds1877 controls and monitors all functions for sff, sfp, and sfp+ modules including all sff-8472 func - tionality. the device supports all los functions for two receivers, and continually monitors for los of either channel. four adc channels monitor v cc , temperature, and two differential external monitor inputs that can be used to meet all monitoring requirements. two digital- to-analog converter (dac) outputs with temperature- indexed lookup tables (luts) are available for additional monitoring and control functionality. applications sff, sfp, and sfp+ transceiver modules dual rx video sfps ordering information features s meets all sff-8472 control and monitoring requirements s four analog monitor channels: temperature, v cc , rssi1, rssi2 rssi1 and rssi2 support internal and external calibration differential input common-mode range from gnd to v cc scalable dynamic range internal direct-to-digital temperature sensor alarm and warning flags for all monitored channels s two 10-bit delta-sigma outputs each controlled by 72-entry temperature lut s digital i/o pins: four inputs, four outputs s comprehensive loss-of-signal (los) detection system s flexible, two-level password scheme provides three levels of security s 120 bytes of password-1 protected memory s 128 bytes of password-2 protected memory in main device address s 256 additional bytes located at a0h slave address s receiver 1 is accessed at a2h slave address s receiver 2 is accessed at b2h slave address s i 2 c-compatible interface s +2.85v to +3.9v operating voltage range s -40 n c to +95 n c operating temperature range s 28-pin tqfn (5mm x 5mm x 0.75mm) package + denotes a lead(pb)-free/rohs-compliant package. t&r = tape and reel. * ep = exposed pad. part temp range pin-package ds1877t+ -40 n c to +95 n c 28 tqfn-ep* ds1877t+t&r -40 n c to +95 n c 28 tqfn-ep*
ds1877 sfp controller for dual rx interface 2 table of contents absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 dac1, dac2 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 analog voltage monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ac electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 analog quick-trip characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 quick-trip timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 digital thermometer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 i 2 c ac electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 nonvolatile memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 typical operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 typical operating circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 detailed description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 dacs during power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 quick-trip timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 monitors and fault detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 monitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 two quick-trip monitors and alarms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 four adc monitors and alarms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 adc timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 right-shifting adc result . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 differential rssi1/rssi2 inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 enhanced rssi monitoring (dual-range functionality) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 crossover enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 crossover disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 low-voltage operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 delta-sigma outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 digital i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 los1, los2, and losout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 inx, rsel, outx, rselout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 fault output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 die identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
ds1877 sfp controller for dual rx interface 3 i 2 c communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 i 2 c definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 i 2 c protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 shadowed eeprom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 memory map access codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 memory addresses a0h, a2h, and b2h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 lower memory register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 01h register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 02h register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 04h register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 05h register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 auxiliary memory a0h register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 lower memory register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 01h register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 02h register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 04h register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 auxiliary memory a0h register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 applications information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 power-supply decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 sda and scl pullup resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table of contents ( continued )
ds1877 sfp controller for dual rx interface 4 list of figures figure 1. power-up timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 2. quick-trip sample timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 3. adc round-robin timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 4. rssi1/rssi2 differential input for high-side rssi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 5. crossover enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 6. crossover disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 7. low-voltage operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 8. recommended rc filter for dac outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 9. 3-bit (8-position) delta-sigma example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 10. dac offset luts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 11. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 12. i 2 c timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 13. example i 2 c timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 14. memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 list of tables table 1. acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 2. adc default monitor full-scale ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 3. rssi1/rssi2 configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 4. rssi1/rssi2 hysteresis threshold values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
ds1877 sfp controller for dual rx interface 5 stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. voltage range on rssi1_, rssi2_, inx, los1, and los2 pins relative to ground ...... -0.5v to (v cc + 0.5v)* voltage range on v cc , sda, scl, outx, fault, rselout, and losout pins relative to ground ....-0.5v to +6v continuous power dissipation 28-pin tqfn (derate 34.5mw/ n c) above +70 n c .... 2758.6mw operating temperature range .......................... -40 n c to +95 n c programming temperature range ....................... 0 n c to +95 n c storage temperature range ............................ -55 n c to +125 n c lead temperature (soldering, 10s) ................................ +300 n c soldering temperature (reflow) ...................................... +260 n c recommended operating conditions (t a = -40 n c to +95 n c, unless otherwise noted.) dc electrical characteristics (v cc = +2.85v to +3.9v, t a = -40 n c to +95 n c, unless otherwise noted.) absolute maximum ratings * subject to not exceeding +6v. parameter symbol conditions min typ max units main supply voltage v cc (note 1) +2.85 +3.9 v high-level input voltage (sda, scl) v ih:1 0.7 x v cc v cc + 0.3 v low-level input voltage (sda, scl) v il:1 -0.3 0.3 x v cc v high-level input voltage (fault, rsel, inx, los1, los2) v ih:2 2.0 v cc + 0.3 v low-level input voltage (fault, rsel, inx, los1, los2) v il:2 -0.3 +0.8 v parameter symbol conditions min typ max units supply current i cc (notes 1, 2) 2.5 10 ma output leakage (sda, outx, rselout, losout, fault) i lo 1 f a low-level output voltage (sda, outx, rselout, losout, dac1, dac2, fault) v ol i ol = 4ma 0.4 v i ol = 6ma 0.6 high-level output voltage (dac1, dac2) v oh i oh = 4ma v cc - 0.4 v dac1 and dac2 before lut recall 10 100 na input leakage current (scl, rsel, inx, los1, los2) i li 1 f a digital power-on reset pod 1.0 2.2 v analog power-on reset poa 2.0 2.75 v
ds1877 sfp controller for dual rx interface 6 dac1, dac2 electrical characteristics (v cc = +2.85v to +3.9v, t a = -40 n c to +95 n c, unless otherwise noted.) analog voltage monitoring characteristics (v cc = +2.85v to +3.9v, t a = -40 n c to +95 n c, unless otherwise noted.) ac electrical characteristics (v cc = +2.85v to +3.9v, t a = -40 n c to +95 n c, unless otherwise noted.) parameter symbol conditions min typ max units main oscillator frequency f osc 5 mhz delta-sigma input-clock frequency f ds f osc /2 mhz reference voltage input (refin) v refin minimum 0.1 f f to gnd 2 v cc v output range 0 v refin v output resolution see the delta-sigma outputs section for details 10 bits output impedance r ds 35 100 i parameter symbol conditions min typ max units adc resolution 13 bits input/supply accuracy (rssi1_, rssi2_, v cc ) acc at factory setting 0.25 0.5 %fs update rate for temperature, rssi1_, rssi2_, v cc t rr 45 75 ms input/supply offset (rssi1_, rssi2_, v cc ) v os (note 3) 0 5 lsb factory setting (note 4) rssi1/rssi2 coarse 2.5 v v cc 6.5536 rssi1/rssi2 fine 312.5 f v parameter symbol conditions min typ max units fault reset time (to fault = 0) t initr from h v cc > vcc lo alarm (note 5) 161 ms losout assert time t loss_on los_ lo (note 6) 25.6 f s losout deassert time t loss_off los_ hi (note 7) 25.6 f s
ds1877 sfp controller for dual rx interface 7 analog quick-trip characteristics (v cc = +2.85v to +3.9v, t a = -40 n c to +95 n c, unless otherwise noted.) quick-trip timing characteristics (v cc = +2.85v to +3.9v, t a = -40 n c to +95 n c, unless otherwise noted.) digital thermometer characteristics (v cc = +2.85v to +3.9v, t a = -40 n c to +95 n c, unless otherwise noted.) i 2 c ac electrical characteristics (v cc = +2.85v to +3.9v, t a = -40 n c to +95 n c, unless otherwise noted. timing is referenced to v il(max) and v ih(min) .) (figure 12) parameter symbol conditions min typ max units rssi full-scale voltage 1.25 v input resistance 35 50 65 k w resolution 8 bits error t a = +25 c 2 %fs integral nonlinearity -1 +1 lsb differential nonlinearity -1 +1 lsb temperature drift -2 +2 %fs offset -5 +10 mv parameter symbol conditions min typ max units output-enable time following poa t init (note 5) 20 ms sample time per quick-trip comparison t rep 12.8 f s parameter symbol conditions min typ max units thermometer error t err -40 n c to +95 n c -3 +3 n c parameter symbol conditions min typ max units scl clock frequency f scl (note 8) 0 400 khz clock pulse-width low t low 1.3 f s clock pulse-width high t high 0.6 f s bus free time between stop and start condition t buf 1.3 f s start hold time t hd:sta 0.6 f s start setup time t su:sta 0.6 f s data out hold time t hd:dat 0 0.9 f s data in setup time t su:dat 100 ns rise time of both sda and scl signals t r (note 9) 20 + 0.1c b 300 ns fall time of both sda and scl signals t f (note 9) 20 + 0.1c b 300 ns stop setup time t su:sto 0.6 f s capacitive load for each bus line c b 400 pf eeprom write time t wr (note 10) 20 ms
ds1877 sfp controller for dual rx interface 8 nonvolatile memory characteristics (v cc = +2.85v to +3.9v, unless otherwise noted.) note 1: all voltages are referenced to ground. current into the ic is positive, and current out of the ic is negative. note 2: inputs are at supply rail. outputs are not loaded. note 3: this parameter is guaranteed by design. note 4: full-scale is user programmable. note 5: a temperature conversion is completed and the dac values are recalled from the luts and v cc has been measured to be above the vcc lo alarm, if the vcc lo alarm is enabled. note 6: this specification is the time it takes from rssi1_ and rssi2_ voltage falling below the llos_ trip threshold to losout asserted high. note 7: this specification is the time it takes from rssi1_ and rssi2_ voltage rising above the hlos_ trip threshold to losout asserted high. note 8: i 2 c interface timing shown is for fast-mode (400khz) operation. this device is also backward compatible with i 2 c stan - dard mode. note 9: c b total capacitance of one bus line in pf. note 10: eeprom write begins after a stop condition occurs. parameter symbol conditions min typ max units eeprom write cycles at +25 n c 200,000 at +85 n c 50,000
ds1877 sfp controller for dual rx interface 9 typical operating characteristics (v cc = +3.3v, t a = +25 n c, unless otherwise noted.) rssi1/rssi2 inl ds1877 toc06 rssi1/rssi2 input voltage (v) rssi1/rssi2 inl (lsb) 2.0 1.5 1.0 0.5 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 0 2.5 using factory-programmed full-scale value of 2.5v rssi1/rssi2 dnl ds1877 toc05 rssi1/rssi2 input voltage (v) rssi1/rssi2 dnl (lsb) 2.0 1.5 1.0 0.5 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 0 2.5 using factory-programmed full-scale value of 2.5v dac1/dac2 inl ds1877 toc04 dac position (dec) dac1/dac2 inl (lsb) 1000 500 -2 -1 0 1 2 3 -3 0 dac1/dac2 dnl ds1877 toc03 dac position (dec) dac1/dac2 dnl (lsb) 1000 500 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 0 supply current vs. temperature ds1877 toc02 temperature (c) supply current (ma) 60 35 10 -15 2.05 2.10 2.15 2.20 2.25 2.30 2.35 2.40 2.45 2.50 2.00 -40 85 dac positions = 1ffh sda = scl = v cc v cc = 3.3v v cc = 3.9v v cc = 2.85v supply current vs. supply voltage ds1877 toc01 v cc (v) supply current (ma) 3.75 3.45 3.15 2.05 2.10 2.15 2.20 2.25 2.30 2.35 2.40 2.45 2.50 2.00 2.85 sda = scl = v cc dacs at 1ffh +95c +25c -40c
ds1877 sfp controller for dual rx interface 10 pin configuration pin description thin qfn (5mm 5mm 0.8mm) top view 26 27 25 24 10 9 11 scl fault los1 inx los2 12 rselout dac1 gnd rssi1n gnd v cc n.c. 1 2 n.c. 4 5 6 7 20 21 19 17 16 15 v cc losout rssi2p n.c. dnc rsel sda dac2 3 18 28 8 outx gnd n.c. 23 13 rssi2n n.c. 22 14 rssi1p refin ds1877 *ep + *exposed pad. pin name function 1 rselout rate-select output 2 scl i 2 c serial-clock input 3 sda i 2 c serial-data input/output 4 fault transmit fault input and output, open drain 5 los1 loss-of-signal input 1 6 inx digital input. general-purpose input, as1 in sff-8079, or rs1 in sff-8431. 7 los2 loss-of-signal input 2 8, 18, 21 gnd ground connection 9 rsel rate-select input 10 dnc do not connect 11, 15, 23, 24, 25 n.c. no connection. not internally connected. pin name function 12, 13 rssi2p, rssi2n differential external monitor input 2 and los2 lo quick trip 14, 17 rssi1p, rssi1n differential external monitor input 1 and los1 lo quick trip 16, 26 v cc power-supply input 19 dac2 dac2, delta-sigma output 20 dac1 dac1, delta-sigma output 22 refin reference input for dac1 and dac2 27 losout receive loss-of-signal output 28 outx digital output. general-purpose output, as1 output in sff-8079, or rs1 output in sff-8431. ep exposed pad (connect to gnd)
ds1877 sfp controller for dual rx interface 11 block diagram analog mux main memory at a2h/b2h eeprom/sram a/d configuration/results, system status/control bits, alarms/warnings, lookup tables, user memory i 2 c interface power-on analog interrupt eeprom 256 bytes at a0h sda scl v cc v cc v cc logic control 10-bit delta-sigma dac 10-bit delta-sigma dac 13-bit adc 8-bit qts temperature sensor dac1 dac2 refin fault rselout rsel inx los1 los2 outx losout gnd ds1877 rssi1p rssi1n rssi2p rssi2n
ds1877 sfp controller for dual rx interface 12 typical operating circuit los1 los1 rout1+ +3.3v rout1- fault dac1 dac2 eeprom los adc sda scl losout fault los los2 mode_def2 (sda) mode_def1 (scl) i 2 c ds1877 rssi1 rssi2 thresh1 r rc filters rx1 los2 rout2+ +3.3v rout2- thresh2 r rx2
ds1877 sfp controller for dual rx interface 13 detailed description the ds1877 integrates the control and monitoring func - tionality required in an sfp or sfp+ system. the device is specifically designed for a dual-receiver sfp module. key components of the device are shown in the block diagram and described in subsequent sections. dacs during power-up on power-up, the device sets the dacs to high imped - ance. after time t init , the dacs are set to an initial con - dition set in eeprom. after a temperature conversion is completed and if the vcc lo alarm is enabled, an addi - tional v cc conversion above the customer-defined vcc lo alarm level is required before the dacs are updated with the value determined by the temperature conversion and the dac lut. see figure 1. quick-trip timing as shown in figure 2, the devices input comparator is shared between two los comparisons. the comparator polls the alarms in a multiplexed sequence. the com - parator checks the los (rssi1_ and rssi2_) signals against the internal reference. depending on the results of the comparison, the corresponding alarms and warn - ings are asserted or deasserted. any qt alarm that is detected by default remains active until a subsequent comparator sample shows that the condition no longer exists. table 1. acronyms figure 1. power-up timing figure 2. quick-trip sample timing v cc v poa dac settings high impedance off state lut value 500s t init quick-trip sample times los2 los1 los1 los2 t rep acronym description adc analog-to-digital converter agc automatic gain control apc automatic power control apd avalanche photodiode atb alarm trap bytes dac digital-to-analog converter los loss of signal lut lookup table nv nonvolatile qt quick trip tia transimpedance amplifier rosa receiver optical subassembly see shadowed eeprom sff small form factor sff-8472 document defining register map of sfps and sffs sfp small form factor pluggable sfp+ enhanced sfp
ds1877 sfp controller for dual rx interface 14 monitors and fault detection monitors monitoring functions on the device include two qt com - parators and four adc channels. this monitoring com - bined with the alarm enables (table 01h/05h) determines when/if the device triggers the fault and/or losout outputs. all the monitoring levels and interrupt masks are user programmable. two quick-trip monitors and alarms two quick-trip monitors are provided that monitor the following: 1) loss of signal 1 (los1 lo) 2) loss of signal 2 (los2 lo) the los_ lo qts compare the rssi_ input against its threshold setting to determine if the present received power is below the specification. the los_ lo qt can be used to set the losout pin. four adc monitors and alarms the adc monitors 4 channels that measure temperature (internal temp sensor), v cc , rssi1, and rssi2 using an analog multiplexer to measure them round-robin with a single adc (see the adc timing section). the 3v chan - nels have a customer-programmable full-scale range, and all channels have a customer-programmable offset value that is factory programmed to a default value (see table 2). additionally, rssi1 and rssi2 can right-shift results by up to 7 bits before the results are compared to alarm thresholds or read over the i 2 c bus. this allows customers with specified adc ranges to calibrate the adc full scale to a factor of 1/2 n of their specified range to measure small signals. the device can then right-shift the results by n bits to maintain the bit weight of their specification (see the right-shifting adc result section). the adc results (after right-shifting, if used) are com - pared to the alarm and warning thresholds after each conversion, and the corresponding alarms are set that can be used to trigger the fault output. these adc thresholds are user programmable, as are the masking registers that can be used to prevent the alarms from triggering the fault output. adc timing there are four analog channels that are digitized in a round-robin fashion in the order as shown in figure 3. the total time required to convert all 4 channels is t rr (see the analog voltage monitoring characteristics for details). right-shifting adc result if the weighting of the adc digital reading must conform to a predetermined full-scale (pfs) value defined by a standards specification (e.g., sff-8472), then right- shifting can be used to adjust the pfs analog measure - ment range while maintaining the weighting of the adc results. the devices range is wide enough to cover all requirements; when the maximum input value is p 1/2 the fs value, right-shifting can be used to obtain greater accuracy. for instance, the maximum voltage might be 1/8 the specified pfs value, so only 1/8 of the converters range is effective over this range. an alternative is to cali - brate the adcs full-scale range to 1/8 the readable pfs value and use a right-shift value of 3. with this implemen - tation, the resolution of the measurement is increased by table 2. adc default monitor full-scale ranges figure 3. adc round-robin timing temp v cc rssi1 fine rssi1 coarse rssi2 fine rssi2 coarse temp one round-robin adc cycle t rr note: if the vcc lo alarm is enabled at power-up, the adc round-robin timing cycles between temperature and v cc only until v cc is above the vcc lo alarm threshold. signal (units) +fs signal +fs hex -fs signal -fs hex temperature ( n c) 127.996 7fff -128 8000 v cc (v) 6.5528 fff8 0 0000 rssi1, rssi2 (v) 2.4997 fff8 0 0000
ds1877 sfp controller for dual rx interface 15 a factor of 8, and because the result is digitally divided by 8 by right-shifting, the bit weight of the measurement still meets the standards specification (i.e., sff-8472). the right-shift operation on the adc result is carried out based on the contents of right-shift control regis - ters (table 02h, registers 8ehC8fh) in eeprom. two analog channelsrssi1 and rssi2each have 3 bits allocated to set the number of right-shifts. up to seven right-shift operations are allowed and are executed as a part of every conversion before the results are compared to the high and low alarm levels, or loaded into their corresponding measurement registers (lower memory, registers 64h to 6bh). this is true during the setup of internal calibration as well as during subsequent data conversions. differential rssi1/rssi2 inputs the device offers fully differential inputs for rssi1 and rssi2. this enables high-side monitoring of rssi, as shown in figure 4. it also reduces board complexity by eliminating the need for a high-side differential amplifier or a current mirror. enhanced rssi monitoring (dual-range functionality) the device offers a feature to improve the accuracy and range of rssi1/rssi2, which is most commonly used for monitoring rssi. using a traditional input, the rssi measurement accuracy can be increased at the cost of reduced input signal swing. the device eliminates this trade-off by offering dual-range calibration on the rssi1/rssi2 channels. the dual-range calibration can operate in two modes: crossover enabled and crossover disabled. dual-range operation is enabled by default (factory programmed in eeprom). however, it can easily be disabled by the rssin_fc and rssin_ff bits (where n can be 1 or 2) in 8dh, table 02h. dual-range functionality consists of two adc modes of operation: fine mode and coarse mode. each mode is calibrated for a unique transfer function, hence the term, dual range. table 3 highlights the registers related to rssi1/rssi2. fine mode is calibrated using the gain, offset, and right-shifting registers at locations shown in table 3, and is ideal for relatively small analog-input voltages. coarse mode is automatically switched to when the input exceeds a threshold. coarse mode is calibrated using different gain and offset registers from fine mode. the gain and offset registers for coarse mode are also shown in table 3. additional information for each of the registers can be found in the memory map (figure 14). table 3. rssi1/rssi2 configuration registers figure 4. rssi1/rssi2 differential input for high-side rssi rssi_p rssi_n adc r rosa v cc ds1877 register fine mode coarse mode rssi1/rssi2 gain (rssi1/2 fine/coarse scale) 9ehC9fh/9ahC9bh, table 02h 9chC9dh/98hC99h, table 02h rssi1/rssi2 offset (rssi1/2 fine/coarse offset) aehCafh/aahCabh, table 02h achCadh/a8hCa9h, table 02h right-shift (rshift 1 , rshift 2 ) 8ehC8fh, table 02h 8ehC8fh, table 02h crossover (xover1/xover2 fine/coarse) a6hCa7h/ 96hC97h , table 02h a4hCa5h/94hC95fh, table 02h force rssi (rssin_fc and rssin_ff bits) 8dh, table 02h update (rssir bit) 6fh, lower memory rssi value (rssi1/rssi2 measurement) 68hC69h, lower memory
ds1877 sfp controller for dual rx interface 16 dual-range operation is transparent to the end user. the results of rssi1/rssi2 adcs are still stored/reported in the same memory locations (68h ? 69h, lower memory) regardless of whether the conversion was performed in fine mode or coarse mode. the rssir bit indicates whether a fine or coarse conversion generated the digital result. when the device is powered up, adcs begin in a round- robin fashion. every rssi1/rssi2 time slice begins with a fine mode adc (using fine modes gain, offset, and right-shifting settings). if the value is too large for a fine conversion, a coarse conversion is performed and the result is reported. the coarse-mode conversion is per - formed using the coarse gain and offset settings. the intersection between coarse and fine depends on the crossover mode used. the rssin_fc and rssin_ff bits are used to force fine-mode or coarse-mode conversions or to disable the dual-range functionality. dual-range functionality is enabled by default (both rssin_fc and rssin_ff are factory programmed to 0 in eeprom). dual-range functionality can be disabled by setting rssin_fc to 0 and rssin_ff to 1. these bits are also useful when cali - brating rssi1/rssi2. see the register descriptions and memory map for additional information. crossover enabled for systems with a nonlinear relationship between the adc input and desired adc result, the mode should be set to crossover enabled (figure 5). the rssi measure - ment of an apd receiver is one such application. using the crossover-enabled mode allows a piecewise linear approximation of the nonlinear response of the apds gain factor. the crossover point is the value where the fine and coarse ranges intersect. the adc result transi - tions between the fine and coarse ranges as defined by the xover registers. right-shifting, slope adjust - ment, and offset are configurable for both the fine and coarse ranges. the xover1/xover2 fine registers determine the maximum results returned by the fine adc conversions before right-shifting. the xover1/ xover2 coarse registers determine the minimum results returned by coarse adc conversions before right-shifting. crossover disabled the crossover-disabled mode is intended for systems with a linear relationship between the rssi1/rssi2 input and the desired adc result. the adc result transitions between the fine and coarse ranges with hysteresis, as shown in figure 6. in crossover-disabled mode, the thresholds between coarse and fine mode are a function of the number of right-shifts being used. with the use of right-shifting, the fine-mode full scale is programmed to (1/2 n ) of the coarse-mode full scale. the device now automatically ranges to choose the range that gives the best resolution for the measurement. table 4 shows the threshold values for each possible number of right-shifts. low-voltage operation the device contains two power-on reset (por) levels. the lower level is a digital por (pod) and the higher level is an analog por (poa). at startup, before the sup - ply voltage rises above poa, the outputs are disabled, all sram locations are set to their defaults, shadowed eeprom (see) locations are zero, and all analog cir - cuitry is disabled. when v cc reaches poa, the see is recalled, and the analog circuitry is enabled. while v cc remains above poa, the device is in its normal operating state, and it responds based on its nonvolatile configu - ration. if during operation v cc falls below poa, but is still above pod, the sram retains the see settings from the first see recall, but the device analog is shut down and the outputs disabled. if the supply voltage recovers back above poa, the device immediately resumes nor - mal operation. if the supply voltage falls below pod, the device sram is placed in its default state and another see recall is required to reload the nonvolatile settings. the eeprom recall occurs the next time v cc next exceeds poa. figure 7 shows the sequence of events as the voltage varies. table 4. rssi1/rssi2 hysteresis threshold values * this is the minimum reported coarse-mode conversion. no. of right- shifts fine mode max (hex) coarse mode min* (hex) 0 fff8 f000 1 7ffc 7800 2 3ffe 3c00 3 1fff 1e00 4 0fff 0f00 5 07ff 0780 6 03ff 03c0 7 01ff 01e0
ds1877 sfp controller for dual rx interface 17 figure 5. crossover enabled figure 6. crossover disabled figure 7. low-voltage operation crossover point rssi result ideal response rssi_ input rssi result fine full-scale response coarse full-scale response fine right-shift = 3 rssi_ input fine coarse hysteresis v poa v pod v cc see recalled value recalled value precharged to 0 precharged to 0 precharged to 0 see recall see recall
ds1877 sfp controller for dual rx interface 18 any time v cc is above pod, the i 2 c interface can be used to determine if v cc is below the poa level. this is accomplished by checking the rdyb bit in the status byte (lower memory, register 6eh). rdyb is set when v cc is below poa; when v cc rises above poa, rdyb is timed (within 500 f s) to go to 0, at which point the part is fully functional. for all device addresses sourced from eeprom (table 02h, register 8bh), the default device address is a2h until v cc exceeds poa, allowing the device address to be recalled from the eeprom. delta-sigma outputs the devices delta-sigma outputs are 10 bits. for illustra - tive purposes, a 3-bit example is provided in figure 8. each possible output of this 3-bit delta-sigma dac is provided in figure 9. in lut mode the dacs are each controlled by an lut with high-temperature resolution and an offset lut with lower temperature resolution. the high-resolution luts each have 2 n c resolutions. the offset luts are located in the upper eight registers (f8hCffh, table 04h) of the table containing each high-resolution lut. the dac values are determined as follows: dac value = dac lut + 4 x (dac offset lut) an example calculation for dac1 is as follows: assumptions: 1) temperature is +43 n c 2) table 04h (dac offset lut), register fch = 2ah 3) table 04h (dac lut), register aah = 7bh because the temperature is +43 n c, the dac lut index is aah and the dac1 offset lut index is fch. dac1 = 7bh + 4 x 2ah = 123h = 291 when temperature controlled, the dacs are updated after each temperature conversion. see figure 10. the reference input, refin, is the supply voltage for the output buffer of all the dacs. the voltage connected to refin must be able to support the edge rate require - ments of the delta-sigma outputs. in a typical applica - tion, a 0.1 f f capacitor should be connected between refin and ground. figure 8. recommended rc filter for dac outputs figure 9. 3-bit (8-position) delta-sigma example ds1877 dac 3.24k ? 3.24k ? 0.01f 0.01f voltage output ds1877 dac 1k ? 1k ? 0.1f 0.1f current sink 2k? o 1 2 3 4 5 6 7
ds1877 sfp controller for dual rx interface 19 digital i/o pins four digital input pins and four digital output pins are provided for monitoring and control. los1, los2, and losout when losc_ = 0 (table 02h, register 8ah), the los_ pin is used to convert a standard comparator output for los to an open-collector output. the output of the mux can be read in the status register (lower memory, register 6eh) as the rxl bit. the rxl signal can be inverted (invlos_ = 1) before driving the open-drain output transistor using the xor gate provided. setting losc_ = 1 configures the mux to be controlled by the los lo qt alarm. the mux setting (stored in eeprom) does not take effect until v cc > poa, allowing the eeprom to recall. inx, rsel, outx, rselout digital input pins inx and rsel primarily serve to meet the rate-select requirements of sfp and sfp+. they can also serve as general-purpose inputs. outx and rselout are driven by a combination of the inx, rsel, and logic dictated by control registers in the eeprom (see figure 11). the levels of inx and rsel can be read from the status register (lower memory, register 6eh). the open-drain output outx can be controlled and/or inverted using the cnfgb register (table 02h, register 89h). the open-drain rselout output is software con - trolled and/or inverted through the status register and figure 10. dac offset luts figure 11. logic diagram dac offset luts (04h)[a2h/b2h] eight registers per dac 0 255 511 delta-sigma dacs 767 1023 each offset register can be independently set between 0 and 1020. 1020 = 4 x ffh. this example illustrates positive and negatve tempco. dac lut bits 7:0 f8h dac lut bits 7:0 f9h dac lut bits 7:0 fah dac lut bits 7:0 fbh dac lut bits 7:0 fch dac lut bits 7:0 fdh dac lut bits 7:0 feh dac lut bits 7:0 ffh 0 255 511 -40c -8c +8c +24c +40c +56c +70c +88c +104c delta-sigma dacs 767 1023 each offset register can be independently set between 0 and 1020. 1020 = 4 x ffh. this example illustrates positive tempco. dac lut bits 7:0 f8h dac lut bits 7:0 f9h dac lut bits 7:0 fah dac lut bits 7:0 fbh dac lut bits 7:0 fch dac lut bits 7:0 fdh dac lut bits 7:0 feh dac lut bits 7:0 ffh dac offset luts (04h)[a2h/b2h] eight registers per dac -40c -8c +8c +24c +40c +56c +70c +88c +104c invoutx inxc inx inxs rxl outx invrsout invlosout losc1 los1 los lo1 invlos1 mux rselout rselc rsel rsels = pins losout los2 invlos2 losc2 los lo2 mux
ds1877 sfp controller for dual rx interface 20 cnfga register (table 02h, register 88h). external pul - lup resistors must be provided on outx and rselout to realize high logic levels. fault output fault can be triggered by all alarms, warnings, and qts. the six adc alarms, warnings, and los qts require enabling (table 01h/05h, registers f8h and fch). latching of the alarms is controlled by the cnfgb and cnfgc registers (table 02h, registers 89h ? 8ah). die identification the device has an id hardcoded in its die. two registers (table 02h, registers 86h ? 87h) are assigned for this feature. register 86h reads 77h to identify the part as the ds1877; register 87h reads the present device version. i 2 c communication i 2 c definitions the following terminology is commonly used to describe i 2 c data transfers. master device: the master device controls the slave devices on the bus. the master device generates scl clock pulses and start and stop conditions. slave devices: slave devices send and receive data at the masters request. bus idle or not busy: time between stop and start conditions when both sda and scl are inac - tive and in their logic-high states. start condition: a start condition is generated by the master to initiate a new data transfer with a slave. transitioning sda from high to low while scl remains high generates a start condition. see figure 12 for applicable timing. stop condition: a stop condition is generated by the master to end a data transfer with a slave. transitioning sda from low to high while scl remains high generates a stop condition. see figure 12 for applicable timing. repeated start condition: the master can use a repeated start condition at the end of one data transfer to indicate that it will immediately initiate a new data transfer following the current one. repeated starts are commonly used during read operations to identify a specific memory address to begin a data transfer. a repeated start condition is issued identi - cally to a normal start condition. see figure 12 for applicable timing. bit write: transitions of sda must occur during the low state of scl. the data on sda must remain valid and unchanged during the entire high pulse figure 12. i 2 c timing scl note: timing is referenced to v il(max) and v ih(min) . sda stop start repeated start t buf t hd:sta t hd:dat t su:dat t su:sto t hd:sta t sp t su:sta t high t r t f t low
ds1877 sfp controller for dual rx interface 21 of scl plus the setup and hold time requirements (figure 12). data is shifted into the device during the rising edge of the scl. bit read: at the end of a write operation, the master must release the sda bus line for the proper amount of setup time (figure 12) before the next rising edge of scl during a bit read. the device shifts out each bit of data on sda at the falling edge of the previous scl pulse and the data bit is valid at the rising edge of the current scl pulse. remember that the master generates all scl clock pulses, including when it is reading bits from the slave. acknowledgement (ack and nack): an acknowl - edgement (ack) or not-acknowledge (nack) is always the 9th bit transmitted during a byte transfer. the device receiving data (the master during a read or the slave during a write operation) performs an ack by transmitting a zero during the 9th bit. a device per - forms a nack by transmitting a one during the 9th bit. timing (figure 12) for the ack and nack is identical to all other bit writes. an ack is the acknowledgment that the device is properly receiving data. a nack is used to terminate a read sequence or as an indication that the device is not receiving data. byte write: a byte write consists of 8 bits of informa - tion transferred from the master to the slave (most significant bit first) plus a 1-bit acknowledgement from the slave to the master. the 8 bits transmitted by the master are done according to the bit write defini - tion and the acknowledgement is read using the bit read definition. byte read: a byte read is an 8-bit information transfer from the slave to the master plus a 1-bit ack or nack from the master to the slave. the 8 bits of information that are transferred (most significant bit first) from the slave to the master are read by the master using the bit read definition, and the master transmits an ack using the bit write definition to receive additional data bytes. the master must nack the last byte read to terminate communication so the slave returns control of sda to the master. slave address byte: each slave on the i 2 c bus responds to a slave address byte sent immediately following a start condition. the slave address byte contains the slave address in the most significant 7 bits and the r/ w bit in the least significant bit. the device responds to three slave addresses. the auxiliary memory always responds to a fixed i 2 c slave address, a0h. (if the main devices slave address is programmed to be a0h/b0h, access to the auxiliary memory is disabled.) the lower memory and tables 00hC05h respond to i 2 c slave addresses whose lower 3 bits are configurable (a0h ? aeh, b0h ? beh) using the device address byte (table 02h, register 8bh). the user also must set the asel bit (table 02h, register 88h) for this address to be active. by writing the correct slave address with r/ w = 0, the master indicates it writes data to the slave. if r/ w = 1, the master reads data from the slave. if an incorrect slave address is written, the device assumes the master is communicating with another i 2 c device and ignores the communications until the next start condition is sent. memory address: during an i 2 c write operation to the device, the master must transmit a memory address to identify the memory location where the slave is to store the data. the memory address is always the second byte transmitted during a write operation following the slave address byte. i 2 c protocol see figure 13 for an example of i 2 c timing. writing a single byte to a slave: the master must generate a start condition, write the slave address byte (r/ w? = 0), write the memory address, write the byte of data, and generate a stop condition. remember that the master must read the slaves acknowledgement during all byte write operations. writing multiple bytes to a slave: to write multiple bytes to a slave, the master generates a start condition, writes the slave address byte (r/ w = 0), writes the memory address, writes up to 8 data bytes, and generates a stop condition. the device writes 1 to 8 bytes (one page or row) with a single write transaction. this is internally controlled by an address counter that allows data to be written to con - secutive addresses without transmitting a memory address before each data byte is sent. the address counter limits the write to one 8-byte page (one row of the memory map). attempts to write to additional pages of memory without sending a stop condition between pages result in the address counter wrap - ping around to the beginning of the present row. for example: a 3-byte write starts at address 06h and writes three data bytes (11h, 22h, and 33h) to three consecutive addresses. the result is that addresses 06h and 07h would contain 11h and 22h, respec - tively, and the third data byte, 33h, would be written to address 00h.
ds1877 sfp controller for dual rx interface 22 to prevent address wrapping from occurring, the master must send a stop condition at the end of the page, then wait for the bus-free or eeprom write time to elapse. then the master can generate a new start condition and write the slave address byte (r/ w = 0) and the first memory address of the next memory row before continuing to write data. acknowledge polling: any time a eeprom page is written, the device requires the eeprom write time (t wr ) after the stop condition to write the contents of the page to eeprom. during the eeprom write time, the device does not acknowledge its slave address because it is busy. it is possible to take advantage of that phenomenon by repeatedly addressing the device, which allows the next page to be written as soon as the device is ready to receive the data. the alternative to acknowledge polling is to wait for maxi - mum period of t wr to elapse before attempting to write again to the device. eeprom write cycles: when eeprom writes occur, the device writes the whole eeprom memory page, even if only a single byte on the page was modified. writes that do not modify all 8 bytes on the page are allowed and do not corrupt the remaining bytes of memory on the same page. because the whole page is written, bytes on the page that were not modified during the transaction are still subject to a write cycle. this can result in a whole page being worn out over time by writing a single byte repeatedly. writing a page 1 byte at a time wears the eeprom out 8x faster than writing the entire page at once. the devices eeprom write cycles are specified in the nonvolatile memory characteristics table. the speci - fication shown is at the worst-case temperature. it can handle approximately 10x that many writes at room temperature. writing to sram-shadowed eeprom memory with seeb = 1 does not count as a eeprom write cycle when evaluating the eeproms estimated lifetime. figure 13. example i 2 c timing start start stop slave ack slave ack stop single-byte write -write 00h to register bah two-byte write -write 01h and 75h to registers c8h and c9h single-byte read -read register bah two-byte read -read c8h and c9h repeated start master nack 1 0 1 0 0 0 1 0 a2h 1 0 1 1 1 0 1 0 bah slave ack start slave ack 1 0 1 0 0 0 1 0 a2h 1 0 1 0 0 0 1 1 a3h 1 0 1 1 1 0 1 0 bah slave ack slave ack stop 0 0 0 0 0 0 0 0 00h stop slave ack stop 0 1 1 1 0 1 0 1 75h start slave ack 1 0 1 0 0 0 1 0 a2h 1 1 0 0 1 0 0 0 c8h slave ack slave ack 0 0 0 0 0 0 0 1 01h slave ack data in bah data repeated start master ack start slave ack 1 0 1 0 0 0 1 0 a2h 1 0 1 0 0 0 1 1 a3h 1 1 0 0 1 0 0 0 c8h slave ack slave ack data in c8h data master nack data in c9h data example i 2 c transactions with a2h as the main memory device address *if asel is 0, the slave address is a0h for the auxiliary memory and a2h/b2h for the main memory. if asel = 1, the slave address is determined by table 02h, register 8bh for the main memory. the auxiliary memory continues to be addressed at a0h, except when the programmed address for the main memory is a0h. typical i 2 c write transaction a) c) b) d) msb lsb b7 b6 b5 b4 b3 b2 b1 b0 register address msb lsb b7 b6 b5 b4 b3 b2 b1 b0 data slave ack slave ack slave address* x x x x 0 0 1 r/w msb lsb read/ write
ds1877 sfp controller for dual rx interface 23 reading a single byte from a slave: unlike the write operation that uses the memory address byte to define where the data is to be written, the read operation occurs at the present value of the memory address counter. to read a single byte from the slave, the master generates a start condition, writes the slave address byte with r/ w = 1, reads the data byte with a nack to indicate the end of the transfer, and generates a stop condition. manipulating the address counter for reads: a dummy write cycle can be used to force the address pointer to a particular value. to do this, the mas - ter generates a start condition, writes the slave address byte (r/ w = 0), writes the memory address where it desires to read, generates a repeated start condition, writes the slave address byte (r/ w = 1), reads data with ack or nack as applicable, and generates a stop condition. memory organization the device features memory tables that are internally organized into 8-byte rows. the main device located at a2h is used for overall device configuration and receiver 1 control, calibration, alarms, warnings, and monitoring. lower memory, a2h is addressed from 00h ? 7fh and contains alarm and warning thresholds, flags, masks, several control registers, password entry area (pwe), and the table-select byte. table 01h, a2h primarily contains user eeprom (with pw1 level access) as well as alarm and warning enable bytes. table 02h, a2h is a multifunction space that contains configuration registers, scaling and offset values, pass - words, and interrupt registers as well as other miscel - laneous control bytes. table 04h, a2h contains a temperature-indexed lut for control of the dac1 voltage. the dac1 lut can be pro - grammed in 2 n c increments over the -40 n c to +102 n c range. it also contains an lut for temperature-controlled offsets for dac1. table 05h, a2h is empty by default. it can be config - ured to contain the alarm and warning enable bytes from table 01h, registers f8h ? ffh with the mask bit enabled (table 02h, register 88h). in this case table 01h is empty. the main device located at b2h is used for receiver 2 control, calibration, alarms, warnings, and monitoring. lower memory, b2h is addressed from 00h ? 7fh and contains alarm and warning thresholds, flags, masks, several control registers, pwe, and the table-select byte. table 01h, b2h contains alarm and warning enable bytes. table 02h, b2h is a multifunction space that contains configuration registers, scaling and offset values, pass - words, interrupt registers as well as other miscellaneous control bytes. table 02h, b2h only contains functions related to receiver 2. all other functions are controlled by table 02h, a2h. table 04h, b2h contains a temperature-indexed lut for control of the dac2 voltage. the dac2 lut can be pro - grammed in 2 n c increments over the -40 n c to +102 n c range. it also contains an lut for temperature-controlled offsets for dac2. table 05h, b2h is empty by default. it can be config - ured to contain the alarm and warning-enable bytes from table 01h, registers f8h ? ffh with the mask bit enabled (table 02h, register 88h). in this case table 01h is empty. auxiliary memory (device a0h) contains 256 bytes of ee memory accessible from address 00h ? ffh. it is selected with the device address of a0h. see the register descriptions section for a more com - plete detail of each bytes function, as well as for read/ write permissions for each byte.
ds1877 sfp controller for dual rx interface 24 shadowed eeprom many nonvolatile memory locations (listed within the register descriptions section) are actually shadowed eeprom and are controlled by the seeb bit in table 02h, register 80h. the device incorporates shadowed eeprom memory locations for key memory addresses that can be writ - ten many times. by default the shadowed eeprom bit, seeb, is not set and these locations act as ordinary eeprom. by setting seeb, these locations function like sram cells, which allow an infinite number of write cycles without concern of wearing out the eeprom. this also eliminates the requirement for the eeprom write time, t wr . because changes made with seeb enabled do not affect the eeprom, these changes are not retained through power cycles. the power-on value is the last value written with seeb disabled. this func - tion can be used to limit the number of eeprom writes during calibration or to change the monitor thresholds periodically during normal operation helping to reduce the number of times eeprom is written. figure 14 shows the memory map and indicates which locations are shadowed eeprom. figure 14. memory map eeprom (256 bytes) ffh i 2 c address a0h i 2 c address a2h/b2h auxiliary device main devices at a2h and b2h 00h alarm- enable row (8 bytes) password entry (pwe) (4 bytes) table-select byte ffh 80h f8h dac1/2 offset lut ffh f8h table 01h eeprom (120 bytes) f7h 7fh 00h lower memory ffh 80h table 02h nonlookup table control and configuration registers (b2h only contains receiver 2- related registers) 80h table 04h dac1 (a2h) dac2 (b2h) lookup table (72 bytes) c7h f8h table 05h alarm-enable row (8 bytes) alarm-enable row can be configured to exist at table 01h or table 05h using mask bit in table 02h, register 88h. ffh note 1: if asel = 0, then the main device i 2 c slave address is a2h/b2h. if asel = 1, then the main device i 2 c slave address is determined by the value in table 02h, register 8bh. a0h and b2h are invalid selections. note 2: table 00h does not exist. note 3: alarm-enable row can be configured to exist at table 01h or table 05h using the mask bit in table 02h, register 88h.
ds1877 sfp controller for dual rx interface 25 register descriptions the register maps show each byte/word (2 bytes) in terms of its row in the memory. the first byte in the row is located in memory at the row address (hexadecimal) in the leftmost column. each subsequent byte on the row is one/two memory locations beyond the previous byte/ words address. a total of 8 bytes are present on each row. for more information about each of these bytes, see the corresponding register description. memory map access codes the following section provides the devices register defi - nitions. each register or row of registers has an access descriptor that determines the password level required to read or write the memory. level 2 password is intend - ed for the module manufacture access only. level 1 password allows another level of protection for items the end consumer wishes to protect. many registers are always readable, but require password access to write. there are a few registers that cannot be read without password access. the following access codes describe each mode the device uses with factory settings for the pw_ena and pw_enb (table 02h, registers c0hCc1h) registers. memory addresses a0h, a2h, and b2h there are three separate i 2 c addresses in the device: a0h, a2h, and b2h. a2h and b2h are used to configure and monitor two receivers. receiver 1 is accessed using a2h. receiver 2 is accessed using b2h. many of the reg - isters in a2h and b2h are shared registers. these reg - isters can be read and written from both a2h and b2h. access code read access write access <0/_> at least 1 byte/bit in the row/byte is different than the rest of the row/byte, so look at each byte/bit separately for permissions. <1/_> read all write pw2 <2/_> read all write not applicable <3/_> read all write all, but the device hardware also writes to these bytes/bits <4/_> read pw2 write pw2 + mode_bit <5/_> read all write all <6/_> read not applicable write all <7/_> read pw1 write pw1 <8/_> read pw2 write pw2 <9/_> read not applicable write pw2 <10/_> read pw2 write not applicable <11/_> read all write pw1 memory code a2h and b2h registers or <_/c> a common memory location is used for a2h and b2h device addresses. reading or writing to these locations is identical, regardless of using a2h or b2h addresses. or <_/d> different memory locations are used for a2h and b2h device addresses. or <_/m> mixture of common and different memory locations for a2h and b2h device address - es. see the individual bytes within the row for clarification. if m is used on an indi - vidual byte, see the expanded bit descrip - tions to determine which bits are common vs. different.
ds1877 sfp controller for dual rx interface 26 lower memory register map or <_/c> = common, or <_/d> = different, or <_/m> = mixture of common and different. table 01h register map or <_/c> = common, or <_/d> = different, or <_/m> = mixture of common and different. note: the alarm enable bytes (registers f8h?ffh) can be configured to exist in table 05h instead of here at table 01h with the mask bit (table 02h, register 88h). if the row is configured to exist in table 05h, these locations are empty in table 01h. the access codes represent the factory default values of pw_ena and pw_enb (table 02h, registers c0h ? c1h). these registers also allow for custom permissions. lower memory row (hex) row name word 0 word 1 word 2 word 3 byte 0/8 byte 1/9 byte 2/a byte 3/b byte 4/c byte 5/d byte 6/e byte 7/f 00C07 <1/c> threshold 0 temp alarm hi temp alarm lo temp warn hi temp warn lo 08C0f <1/c > threshold 1 v cc alarm hi v cc alarm lo v cc warn hi v cc warn lo 10C1f <1/c> eeprom ee ee ee ee 20C27 <1/d> threshold 4 rssi alarm hi rssi alarm lo rssi warn hi rssi warn lo 28C37 <1/c > eeprom ee ee ee ee 38C4f <1/d > eeprom ee ee ee ee 50C5f <1/c > eeprom ee ee ee ee ee ee ee ee 60C67 <2/c> adc values 0 temp value v cc value reserved reserved 68C6f <0/m> adc values 1 <2/d> rssi value reserved reserved <0/m> status <3/d> update 70C77 <2/d> alarm/warn alarm 3 alarm 2 reserved alarm 0 warn 3 reserved reserved reserved 78C7f <0/m> table select reserved reserved reserved <6/c> pwe msw <6/c> pwe lsw <5/d> tbl sel table 01h row (hex) row name word 0 word 1 word 2 word 3 byte 0/8 byte 1/9 byte 2/a byte 3/b byte 4/c byte 5/d byte 6/e byte 7/f 80Cbf <7/c> eeprom ee ee ee ee ee ee ee ee c0Cf7 <8/c> eeprom ee ee ee ee ee ee ee ee f8Cff <7/m> alarm enable alarm en 3 alarm en 2 reserved alarm en 0 warn en 3 reserved reserved reserved access code <0/_> <1/_> <2/_> <3/_> <4/_> <5/_> <6/_> <7/_> <8/_> <9/_> <10/_> <11/_> read access see each bit/byte separately all all all pw2 all n/a pw1 pw2 n/a pw2 all write access pw2 n/a all and ds1877 hardware pw2 + mode bit all all pw1 pw2 pw2 n/a pw1
ds1877 sfp controller for dual rx interface 27 table 02h register map or <_/c> = common, or <_/d> = different, or <_/m> = mixture of common and different. * the final result must be xored with bb40h before writing to this register. table 04h register map or <_/c> = common, or <_/d> = different, or <_/m> = mixture of common and different. the access codes represent the factory default values of pw_ena and pw_enb (table 02h, registers c0h ? c1h). these registers also allow for custom permissions. access code <0/_> <1/_> <2/_> <3/_> <4/_> <5/_> <6/_> <7/_> <8/_> <9/_> <10/_> <11/_> read access see each bit/byte separately all all all pw2 all n/a pw1 pw2 n/a pw2 all write access pw2 n/a all and ds1877 hardware pw2 + mode bit all all pw1 pw2 pw2 n/a pw1 table 02h (pw2) row (hex) row name word 0 word 1 word 2 word 3 byte 0/8 byte 1/9 byte 2/a byte 3/b byte 4/c byte 5/d byte 6/e byte 7/f 80 <0/c> config 0 <8/c> mode <4/c> tindex reserved reserved reserved reserved <10> device id <10> device ver 88 <8/c> config 1 cnfga cnfgb cnfgc device address reserved force rssi rshift 2 rshift 1 90 <8/c> scale 0 reserved v cc scale xover2 coarse xover2 fine 98 <8/c> scale 1 rssi2 coarse scale rssi2 fine scale rssi1 coarse scale rssi1 fine scale a0 <8/c> offset 0 internal temp offset* v cc offset xover1 coarse xover1 fine a8 <8/c> offset 1 rssi2 coarse offset rssi2 fine offset rssi1 coarse offset rssi1 fine offset b0 <9/c> pwd value pw1 msw pw1 lsw pw2 msw pw2 lsw b8 <8/c> threshold los ranging 2 reserved hlos2 llos2 los ranging 1 reserved hlos1 llos1 c0 <8/c> pwd enable pw_ena pw_enb reserved reserved reserved reserved polarity tblselpon c8 <4/c> dac values dac2 value reserved dac1 value reserved d0Cff empty empty empty empty empty empty empty empty empty table 04h (dac lut) row (hex) row name word 0 word 1 word 2 word 3 byte 0/8 byte 1/9 byte 2/a byte 3/b byte 4/c byte 5/d byte 6/e byte 7/f 80Cc7 <8/d> lut4 dac lut dac lut dac lut dac lut dac lut dac lut dac lut dac lut c8Cf7 empty empty empty empty empty empty empty empty empty f8Cff <8/d> dac offset dac offset lut dac offset lut dac offset lut dac offset lut dac offset lut dac offset lut dac offset lut dac offset lut
ds1877 sfp controller for dual rx interface 28 table 05h register map or <_/c> = common, or <_/d> = different, or <_/m> = mixture of common and different. note: table 05h is empty by default. it can be configured to contain the alarm and warning enable bytes from table 01h, registers f8h?ffh with the mask bit enabled (table 02h, register 88h). in this case table 01h is empty. auxiliary memory a0h register map the access codes represent the factory default values of pw_ena and pw_enb (table 02h, registers c0h ? c1h). these registers also allow for custom permissions. or <_/c> = common, or <_/d> = different, or <_/m> = mixture of common and different. table 05h row (hex) row name word 0 word 1 word 2 word 3 byte 0/8 byte 1/9 byte 2/a byte 3/b byte 4/c byte 5/d byte 6/e byte 7/f 80Cf7 empty empty empty empty empty empty empty empty empty f8Cff <7/m> alarm enable alarm en 3 alarm en 2 reserved alarm en 0 warn en 3 reserved reserved reserved auxiliary memory (a0h) row (hex) row name word 0 word 1 word 2 word 3 byte 0/8 byte 1/9 byte 2/a byte 3/b byte 4/c byte 5/d byte 6/e byte 7/f 00Cff <5> aux ee ee ee ee ee ee ee ee ee access code <0/_> <1/_> <2/_> <3/_> <4/_> <5/_> <6/_> <7/_> <8/_> <9/_> <10/_> <11/_> read access see each bit/byte separately all all all pw2 all n/a pw1 pw2 n/a pw2 all write access pw2 n/a all and ds1877 hardware pw2 + mode bit all all pw1 pw2 pw2 n/a pw1
ds1877 sfp controller for dual rx interface 29 lower memory register descriptions lower memory, register 00h C 01h: temp alarm hi lower memory, register 04h C 05h: temp warn hi lower memory, register 02h C 03h: temp alarm lo lower memory, register 06h C 07h: temp warn lo factory default 7fffh read access all write access pw2 or (pw1 and wlower) a2h and b2h memory common a2h and b2h memory locations memory type nonvolatile (see) 00h, 04h s 2 6 2 5 2 4 2 3 2 2 2 1 2 0 01h, 05h 2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 2 -8 bit 7 bit 0 temperature measurement updates above this twos complement threshold set its corresponding alarm or warn - ing bit. temperature measurement updates equal to or below this threshold clear its alarm or warning bit. factory default 8000h read access all write access pw2 or (pw1 and wlower) a2h and b2h memory common a2h and b2h memory locations memory type nonvolatile (see) 02h, 06h s 2 6 2 5 2 4 2 3 2 2 2 1 2 0 03h, 07h 2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 2 -8 bit 7 bit 0 temperature measurement updates below this twos complement threshold set its corresponding alarm or warn - ing bit. temperature measurement updates equal to or above this threshold clear its alarm or warning bit.
ds1877 sfp controller for dual rx interface 30 lower memory, register 10h C 1fh: ee lower memory, register 08h C 09h: v cc alarm hi lower memory, register 0ch C 0dh: v cc warn hi lower memory, register 0ah C 0bh: v cc alarm lo lower memory, register 0eh C 0fh: v cc warn lo factory default ffffh read access all write access pw2 or (pw1 and wlower) a2h and b2h memory common a2h and b2h memory locations memory type nonvolatile (see) 08h, 0ch 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 09h, 0dh 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 voltage measurement updates above this unsigned threshold set its corresponding alarm or warning bit. voltage measurements equal to or below this threshold clear its alarm or warning bit. factory default 0000h read access all write access pw2 or (pw1 and wlower) a2h and b2h memory common a2h and b2h memory locations memory type nonvolatile (see) 0ah, 0eh 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 0bh, 0fh 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 voltage measurement updates below this unsigned threshold set its corresponding alarm or warning bit. voltage measurements equal to or above this threshold clear its alarm or warning bit. factory default 00h read access all write access pw2 or (pw1 and wlower) a2h and b2h memory common a2h and b2h memory locations memory type nonvolatile (ee) 10hC1fh ee ee ee ee ee ee ee ee bit 7 bit 0 pw2 level access-controlled eeprom.
ds1877 sfp controller for dual rx interface 31 lower memory, register 20h C 21h: rssi alarm hi lower memory, register 24h C 25h: rssi warn hi lower memory, register 22h C 23h: rssi alarm lo lower memory, register 26h C 27h: rssi warn lo factory default ffffh read access all write access pw2 or (pw1 and wlower) a2h and b2h memory different a2h and b2h memory locations memory type nonvolatile (see) 20h, 24h 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 21h, 25h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 voltage measurement updates above this unsigned threshold set its corresponding alarm or warning bit. voltage measurements equal to or below this threshold clear its alarm or warning bit. factory default 0000h read access all write access pw2 or (pw1 and wlower) a2h and b2h memory different a2h and b2h memory locations memory type nonvolatile (see) 22h, 26h 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 23h, 27h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 voltage measurement updates below this unsigned threshold set its corresponding alarm or warning bit. voltage measurements equal to or above this threshold clear its alarm or warning bit.
ds1877 sfp controller for dual rx interface 32 lower memory, register 28h C 37h: ee lower memory, register 38h C 4fh: ee lower memory, register 50h C 5fh: ee factory default 00h read access all write access pw2 or (pw1 and wlower) a2h and b2h memory common a2h and b2h memory locations memory type nonvolatile (ee) 28hC37h ee ee ee ee ee ee ee ee bit 7 bit 0 pw2 level access-controlled eeprom. factory default 00h read access all write access pw2 or (pw1 and wlower) a2h and b2h memory different a2h and b2h memory locations memory type nonvolatile (ee) 38hC4fh ee ee ee ee ee ee ee ee bit 7 bit 0 pw2 level access-controlled eeprom. factory default 00h read access all write access pw2 or (pw1 and wlower) a2h and b2h memory common a2h and b2h memory locations memory type nonvolatile (ee) 50hC5fh ee ee ee ee ee ee ee ee bit 7 bit 0 pw2 level access-controlled eeprom.
ds1877 sfp controller for dual rx interface 33 lower memory, register 60h C 61h: temp value lower memory, register 62h C 63h: v cc value lower memory, register 64h C 67h: reserved power-on value 0000h read access all write access n/a a2h and b2h memory common a2h and b2h memory locations memory type volatile 60h s 2 6 2 5 2 4 2 3 2 2 2 1 2 0 61h 2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 2 -8 bit 7 bit 0 signed twos complement direct-to-temperature measurement. power-on value 0000h read access all write access n/a a2h and b2h memory common a2h and b2h memory locations memory type volatile 62h 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 63h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 left-justified unsigned voltage measurement. power-on value 00h read access n/a write access n/a a2h and b2h memory n/a memory type n/a 64hC67h 0 0 0 0 0 0 0 0 bit 7 bit 0 these registers are reserved. the value when read is 00h.
ds1877 sfp controller for dual rx interface 34 lower memory, register 68h C 69h: rssi value lower memory, register 6ah C 6dh: reserved power-on value 0000h read access all write access n/a a2h and b2h memory different a2h and b2h memory locations memory type volatile 68h 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 69h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 left-justified unsigned voltage measurement. power-on value 00h read access n/a write access n/a a2h and b2h memory n/a memory type n/a 6ahC6dh 0 0 0 0 0 0 0 0 bit 7 bit 0 these registers are reserved. the value when read is 00h.
ds1877 sfp controller for dual rx interface 35 lower memory, register 6eh: status power-on value x0xx 0xxxb read access all write access see below a2h and b2h memory mixture of common memory locations and different memory locations (see below) memory type volatile write access n/a all n/a all all n/a n/a n/a 6eh reserved <5/d> txdc <2/c> inxs <2/c> rsels <5/c> rselc <2/c> flts <2/d> rxl <2/c> rdyb bit 7 bit 0 bit 7 reserved bit 6 txdc1 [a2h]: txd1 software control bit (writable by all users). 0 = (default) this bit has no effect on alarms and warnings. 1 = setting txdc1 inhibits the latching of low alarms and warnings los1 lo, los2 lo, rssi1 lo, and rssi2 lo after the condition is cleared. once txdc1 is set, it is internally extended by time t initr to allow for settings to stabilize. clearing txdc1 before t initr has no impact on the latching of these alarms and warnings. txdc2 [b2h]: txd2 software control bit (writable by all users). 0 = (default) this bit has no effect on alarms and warnings. 1 = setting txdc2 inhibits the latching of low alarms and warnings los1 lo, los2 lo, rssi1 lo, and rssi2 lo after the condition is cleared. once txdc2 is set, it is internally extended by time t initr to allow for settings to stabilize. clearing txdc2 before t initr has no impact on the latching of these alarms and warnings. bit 5 inxs [a2h or b2h]: inx status bit. reflects the logic state of the inx pin (read-only). 0 = inx pin is logic-low. 1 = inx pin is logic-high. bit 4 rsels [a2h or b2h]: rsel status bit. reflects the logic state of the rsel pin (read-only). 0 = rsel pin is logic-low. 1 = rsel pin is logic-high. bit 3 rselc [a2h or b2h]: rsel software control bit. this bit allows for software control that is iden - tical to the rsel pin. its value is wire-ored with the logic value of the rsel pin to create the rselout pins logic value (writable by all users). 0 = (default) 1 = forces the device into a rsel state regardless of the value of the rsel pin. bit 2 flts: reflects the driven state of the fault pin (read-only). 0 = fault pin is low. 1 = fault pin is high. bit 1 rxl1 [a2h]: status of los1 pin or los1 lo as determined by the losc control bit. rxl2 [b2h]: status of los2 pin or los2 lo as determined by the losc control bit. bit 0 rdyb [a2h or b2h]: ready bar. 0 = v cc is above poa. 1 = v cc is below poa and/or too low to communicate over the i 2 c bus.
ds1877 sfp controller for dual rx interface 36 lower memory, register 70h: alarm 3 lower memory, register 6fh: update power-on value 00h read access all write access all and device hardware a2h and b2h memory different a2h and b2h memory locations memory type volatile 6fh temp rdy vcc rdy reserved reserved rssi rdy reserved reserved rssir bit 7 bit 0 bits 7, 6, 3 temp rdy, vcc rdy, rssi rdy: update of completed conversions. at power-on, these bits are cleared and are set as each conversion is completed. these bits can be cleared so that a completion of a new conversion is verified. bits 5, 4, 2, 1 reserved bit 0 rssir: rssi range. reports the range used for conversion update of rssi. 0 = fine range is the reported value. 1 = coarse range is the reported value. power-on value 10h read access all write access n/a a2h and b2h memory different a2h and b2h memory locations memory type volatile 70h temp hi temp lo vcc hi vcc lo reserved reserved reserved reserved bit 7 bit 0 bit 7 temp hi: high alarm status for temperature measurement. 0 = (default) last measurement was equal to or below threshold setting. 1 = last measurement was above threshold setting. bit 6 temp lo: low alarm status for temperature measurement. 0 = (default) last measurement was equal to or above threshold setting. 1 = last measurement was below threshold setting. bit 5 vcc hi: high alarm status for v cc measurement. 0 = (default) last measurement was equal to or below threshold setting. 1 = last measurement was above threshold setting. bit 4 vcc lo: low alarm status for v cc measurement. this bit is set when the v cc supply is below the poa trip point value. it clears itself when a v cc measurement is completed and the value is above the low threshold. 0 = last measurement was equal to or above threshold setting. 1 = (default) last measurement was below threshold setting. bits 3:0 reserved
ds1877 sfp controller for dual rx interface 37 lower memory, register 71h: alarm 2 lower memory, register 72h: reserved power-on value 00h read access all write access n/a a2h and b2h memory mixed a2h and b2h memory locations memory type volatile 71h rssi hi rssi lo reserved reserved reserved reserved reserved fltint bit 7 bit 0 bit 7 rssi hi: high alarm status for rssi measurement. a txd event does not clear this alarm. 0 = (default) last measurement was equal to or below the threshold setting. 1 = last measurement was above the threshold setting. bit 6 rssi lo: low alarm status for rssi measurement. a txd event does not clear this alarm. 0 = (default) last measurement was equal to or above the threshold setting. 1 = last measurement was below the threshold setting. bits 5:1 reserved bit 0 fltint: fault interrupt. this bit is the wire-ored logic of all alarms and warnings wire-anded with their corresponding enable bits. the enable bits are found in table 01h/05h, registers f8hCffh. power-on value 00h read access n/a write access n/a a2h and b2h memory n/a memory type n/a this register is reserved.
ds1877 sfp controller for dual rx interface 38 lower memory, register 73h: alarm 0 lower memory, register 74h: warn 3 power-on value 00h read access all write access n/a a2h and b2h memory different a2h and b2h memory locations memory type volatile 73h los hi los lo reserved reserved reserved reserved reserved reserved bit 7 bit 0 bit 7 los hi: high alarm status for rssi; fast comparison. a txd event does not clear this alarm. 0 = (default) last comparison was below threshold setting. 1 = last comparison was above threshold setting. bit 6 los lo: low alarm status for rssi; fast comparison. a txd event does not clear this alarm. 0 = (default) last comparison was above threshold setting. 1 = last comparison was below threshold setting. bits 5:0 reserved power-on value 10h read access all write access n/a a2h and b2h memory different a2h and b2h memory locations memory type volatile 74h temp hi temp lo vcc hi vcc lo reserved reserved reserved reserved bit 7 bit 0 bit 7 temp hi: high warning status for temperature measurement. 0 = (default) last measurement was equal to or below threshold setting. 1 = last measurement was above threshold setting. bit 6 temp lo: low warning status for temperature measurement. 0 = (default) last measurement was equal to or above threshold setting. 1 = last measurement was below threshold setting. bit 5 vcc hi: high warning status for v cc measurement. 0 = (default) last measurement was equal to or below threshold setting. 1 = last measurement was above threshold setting. bit 4 vcc lo: low warning status for v cc measurement. this bit is set when the v cc supply is below the poa trip-point value. it clears itself when a v cc measurement is completed and the value is above the low threshold. 0 = last measurement was equal to or above threshold setting. 1 = (default) last measurement was below threshold setting. bits 3:0 reserved
ds1877 sfp controller for dual rx interface 39 lower memory, register 7fh: table select (tbl sel) lower memory, registers 75h C 7ah: reserved lower memory, registers 7bh C 7eh: password entry (pwe) power-on value 00h read access n/a write access n/a a2h and b2h memory n/a memory type n/a these registers are reserved. the value when read is 00h. power-on value ffff ffffh read access n/a write access all a2h and b2h memory common a2h and b2h memory locations memory type volatile 7bh 2 31 2 30 2 29 2 28 2 27 2 26 2 25 2 24 7ch 2 23 2 22 2 21 2 20 2 19 2 18 2 17 2 16 7dh 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 7eh 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 there are two passwords for the device. each password is 4 bytes long. the lower level password (pw1) has all the access of a normal user plus those made available with pw1. the higher level password (pw2) has all the access of pw1 plus those made available with pw2. the values of the passwords reside in eeprom inside pw2 memory. at power-up, all pwe bits are set to 1. all reads at this location are 0. power-on value tblselpon (table 02h, register c7h) read access all write access all a2h and b2h memory different a2h and b2h memory locations memory type volatile 7fh 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 the upper memory tables of the device are accessible by writing the desired table value in this register. the power- on value of this register is defined by the value written to tblselpon (table 02h, register c7h).
ds1877 sfp controller for dual rx interface 40 table 01h register descriptions table 01h, register 80h C f7h: eeprom table 01h, register f8h: alarm en 3 power-on value 00h read access pw2 or (pw1 and rwtbl1a) or (pw1 and rtbl1a) write access pw2 or (pw1 and rwtbl1a) a2h and b2h memory common a2h and b2h memory locations memory type nonvolatile (ee) 80hCf7h ee ee ee ee ee ee ee ee bit 7 bit 0 eeprom for pw1 and/or pw2 level access. power-on value 00h read access pw2 or (pw1 and rwtbl1c) or (pw1 and rtbl1c) write access pw2 or (pw1 and rwtbl1c) a2h and b2h memory common a2h and b2h memory locations memory type nonvolatile (see) f8h temp hi temp lo vcc hi vcc lo reserved reserved reserved reserved bit 7 bit 0 layout is identical to alarm 3 in lower memory, register 70h. enables alarms to create fltint (lower memory, register 71h) logic. the mask bit (table 02h, register 88h) determines whether this memory exists in table 01h or 05h. bit 7 temp hi [a2h or b2h]: 0 = disables interrupt from temp hi alarm. 1 = enables interrupt from temp hi alarm. bit 6 temp lo [a2h or b2h]: 0 = disables interrupt from temp lo alarm. 1 = enables interrupt from temp lo alarm. bit 5 vcc hi [a2h or b2h]: 0 = disables interrupt from vcc hi alarm. 1 = enables interrupt from vcc hi alarm. bit 4 vcc lo [a2h or b2h]: 0 = disables interrupt from vcc lo alarm. 1 = enables interrupt from vcc lo alarm. bits 3:0 reserved
ds1877 sfp controller for dual rx interface 41 table 01h, register f9h: alarm en 2 table 01h, register fah: reserved power-on value 00h read access pw2 or (pw1 and rwtbl1c) or (pw1 and rtbl1c) write access pw2 or (pw1 and rwtbl1c) a2h and b2h memory different a2h and b2h memory locations memory type nonvolatile (see) f9h rssi hi rssi lo reserved reserved reserved reserved reserved reserved bit 7 bit 0 layout is identical to alarm 2 in lower memory, register 71h. enables alarms to create fltint (lower memory, register 71h). the mask bit (table 02h, register 88h) determines whether this memory exists in table 01h or 05h. bit 7 rssi hi: 0 = disables interrupt from rssi hi alarm. 1 = enables interrupt from rssi hi alarm. bit 6 rssi lo: 0 = disables interrupt from rssi lo alarm. 1 = enables interrupt from rssi lo alarm. bits 5:0 reserved power-on value 00h read access n/a write access n/a a2h and b2h memory n/a memory type n/a this register is reserved.
ds1877 sfp controller for dual rx interface 42 table 01h, register fbh: alarm en 0 table 01h, register fch: warn en 3 power-on value 00h read access pw2 or (pw1 and rwtbl1c) or (pw1 and rtbl1c) write access pw2 or (pw1 and rwtbl1c) a2h and b2h memory different a2h and b2h memory locations memory type nonvolatile (see) fbh los hi los lo reserved reserved reserved reserved reserved reserved bit 7 bit 0 layout is identical to alarm 0 in lower memory, register 73h. the mask bit (table 02h, register 88h) determines whether this memory exists in table 01h or 05h. bit 7 los hi: enables alarm to create fltint (lower memory, register 71h) logic. 0 = disables interrupt from los hi alarm. 1 = enables interrupt from los hi alarm. bit 6 los lo: enables alarm to create fltint (lower memory, register 71h) logic. 0 = disables interrupt from los lo alarm. 1 = enables interrupt from los lo alarm. bits 5:0 reserved power-on value 00h read access pw2 or (pw1 and rwtbl1c) or (pw1 and rtbl1c) write access pw2 or (pw1 and rwtbl1c) a2h and b2h memory common a2h and b2h memory locations memory type nonvolatile (see) fch temp hi temp lo vcc hi vcc lo reserved reserved reserved reserved bit 7 bit 0 layout is identical to warn 3 in lower memory, register 74h. enables warnings to create fltint (lower memory, register 71h) logic. the mask bit (table 02h, register 88h) determines whether this memory exists in table 01h or 05h. bit 7 temp hi [a2h or b2h]: 0 = disables interrupt from the temp hi warning. 1 = enables interrupt from the temp hi warning. bit 6 temp lo [a2h or b2h]: 0 = disables interrupt from the temp lo warning. 1 = enables interrupt from the temp lo warning. bit 5 vcc hi [a2h or b2h]: 0 = disables interrupt from the vcc hi warning. 1 = enables interrupt from the vcc hi warning. bit 4 vcc lo [a2h or b2h]: 0 = disables interrupt from the vcc lo warning. 1 = enables interrupt from the vcc lo warning. bits 3:0 reserved
ds1877 sfp controller for dual rx interface 43 table 01h, register fdh C ffh: reserved table 02h register descriptions table 02h, register 80h: mode power-on value 00h read access n/a write access n/a a2h and b2h memory n/a memory type n/a these registers are reserved. power-on value 7fh read access pw2 or (pw1 and rwtbl2) or (pw1 and rtbl2) write access pw2 or (pw1 and rwtbl2) a2h and b2h memory common a2h and b2h memory locations memory type volatile 80h seeb dac2en reserved reserved aen dac1en reserved reserved bit 7 bit 0 bit 7 seeb: 0 = (default) enables eeprom writes to see bytes. 1 = disables eeprom writes to see bytes during configuration, so that the configuration of the part is not delayed by the ee cycle time. once the values are known, write this bit to a 0 and write the see locations again for data to be written to the eeprom. bit 6 dac2en: 0 = dac2 value is writable by the user and the lut recalls are disabled. this allows users to interactively test their modules by writing the values for dac2. the output is updated with the new value at the end of the write cycle. the i 2 c stop condition is the end of the write cycle. 1 = (default) enables automatic control of the lut for dac2 value. bits 5, 4, 1, 0 reserved bit 3 aen: 0 = the temperature-calculated index value tindex is writable by the user and the updates of cal - culated indexes are disabled. this allows the user to interactively test the modules by controlling the indexing for the luts. the recalled values from the luts appear in the dac registers after the next completion of a temperature conversion. 1 = (default) the temperature-calculated index value tindex is used to control the luts. bit 2 dac1en: 0 = dac1 value is writable by the user and the lut recalls are disabled. this allows the user to interactively test their modules by writing the values for dac1. the output is updated with the new value at the end of the write cycle. the i 2 c stop condition is the end of the write cycle. 1 = (default) enables automatic control of the lut for dac1 value.
ds1877 sfp controller for dual rx interface 44 table 02h, register 81h: temperature index (tindex) table 02h, register 82h C 85h: reserved table 02h, register 86h: device id factory default 00h read access pw2 or (pw1 and rwtbl2) or (pw1 and rtbl2) write access (pw2 and aen = 0) or (pw1 and rwtbl2 and aen = 0) a2h and b2h memory common a2h and b2h memory locations memory type volatile 81h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 holds the calculated index based on the temperature measurement. this index is used for the address during lookup of table 04h. temperature measurements below -40 n c or above +102 n c are clamped to 80h and c7h, respectively. the calculation of tindex is as follows: temp_value 40 c tindex 80h 2 c + = + for the temperature-indexed luts (2 n c), the index used during the lookup function for each table is as follows: table 04h (dac) 1 tindex 6 tindex 5 tindex 4 tindex 3 tindex 2 tindex 1 tindex 0 for the 8-position lut tables, the following table shows the lookup function: tindex 1000_0xxx 1001_0xxx 1001_1xxx 1010_0xxx 1010_1xxx 1011_0xxx 1011_1xxx 11xx_xxxx byte f8 f9 fa fb fc fd fe ff temp ( n c) < -8 -8 to +8 +8 to +24 +24 to +40 +40 to +56 +56 to +72 +72 to +88 r +88 factory default 00h read access n/a write access n/a a2h and b2h memory n/a memory type n/a these registers are reserved. factory default 77h read access pw2 or (pw1 and rwtbl2) or (pw1 and rtbl2) write access n/a memory type rom 86h 0 1 1 1 0 1 1 1 bit 7 bit 0 hardwired connections to show the device id.
ds1877 sfp controller for dual rx interface 45 table 02h, register 87h: device ver table 02h, register 88h: cnfga factory default device version read access pw2 or (pw1 and rwtbl2) or (pw1 and rtbl2) write access n/a memory type rom 87h device version bit 7 bit 0 hardwired connections to show the device version. factory default c0h read access pw2 or (pw1 and rwtbl2) or (pw1 and rtbl2) write access pw2 or (pw1 and rwtbl2) a2h and b2h memory common a2h and b2h memory locations memory type nonvolatile (see) 88h reserved reserved reserved asel mask invrsout reserved invlosout bit 7 bit 0 bits 7:5, 1 reserved bit 4 asel: address select. 0 = (default) device address is a2h for receiver 1 and b2h for receiver 2. 1 = device address byte (table 02h, register 8bh) is used as the device address for receiver 1. receiver 2 remains at b2h. bit 3 mask: 0 = (default) alarm-enable row exists at table 01h, registers f8hCffh. table 05h, registers f8hC ffh are empty. 1 = alarm-enable row exists at table 05h, registers f8hCffh. table 01h, registers f8hCffh are empty. bit 2 invrsout: allow for inversion of the rselout pin (see figure 11). 0 = (default) rselout is not inverted. 1 = rselout is inverted. bit 0 invlosout: allow for inversion of signal driven to the losout output pin. 0 = (default) losout is not inverted. 1 = losout signal is inverted.
ds1877 sfp controller for dual rx interface 46 table 02h, register 89h: cnfgb factory default 00h read access pw2 or (pw1 and rwtbl2) or (pw1 and rtbl2) write access pw2 or (pw1 and rwtbl2) a2h and b2h memory common a2h and b2h memory locations memory type nonvolatile (see) 89h inxc invoutx alatch2 qtlatch2 wlatch2 alatch1 qtlatch1 wlatch1 bit 7 bit 0 bit 7 inxc: inx software control bit (see figure 11). 0 = inx pins logic controls outx pin. 1 = outx is active (bit 6 defines the polarity). bit 6 invoutx: inverts the active state for outx (see figure 11). 0 = noninverted. 1 = inverted. bit 5 alatch2: adc alarms comparison latch, lower memory, registers 70hC71h. 0 = adc alarm and flags reflect the status of the last comparison. 1 = adc alarm flags remain set. bit 4 qtlatch2: qts comparison latch, lower memory, register 73h. 0 = qt alarm and warning flags reflect the status of the last comparison. 1 = qt alarm and warning flags remain set. bit 3 wlatch2: adc warnings comparison latch, low er memory, register 74h. 0 = adc warning flags reflect the status of the last comparison. 1 = adc warning flags remain set. bit 2 alatch1: adc alarms comparison latch, lower memory, registers 70hC71h. 0 = adc alarm and flags reflect the status of the last comparison. 1 = adc alarm flags remain set. bit 1 qtlatch1: qts comparison latch, lower memory, register 73h. 0 = qt alarm and warning flags reflect the status of the last comparison. 1 = qt alarm and warning flags remain set. bit 0 wlatch1: adc warnings comparison latch, lower memory, register 74h. 0 = adc warning flags reflect the status of the last comparison. 1 = adc warning flags remain set.
ds1877 sfp controller for dual rx interface 47 table 02h, register 8ah: cnfgc table 02h, register 8bh: device address factory default 00h read access pw2 or (pw1 and rwtbl2) or (pw1 and rtbl2) write access pw2 or (pw1 and rwtbl2) a2h and b2h memory common a2h and b2h memory locations memory type nonvolatile (see) 8ah reserved txd_rst en dac2 losc2 invlos2 reserved txd_rst en dac1 losc1 invlos1 bit 7 bit 0 bits 7, 3 reserved bit 6 txd_rst en dac2: 0 = txdc2 has no effect on dac2. 1 = dac2 is reset by txdc2. bit 5 losc2: see figure 11. 0 = los2 lo qt drives losout logic. 1 = los2 input pin drives losout logic. bit 4 invlos2: see figure 11. 0 = (default) los2 input is not inverted. 1 = los2 input is inverted. bit 2 txd_rst en dac1: see figure 11. 0 = txdc1 has no effect on dac1. 1 = dac1 is reset by txdc1. bit 1 losc1: see figure 11. 0 = los1 lo qt drives losout logic. 1 = los1 input pin drives losout logic. bit 0 invlos1: see figure 11. 0 = (default) los1 input is not inverted. 1 = los1 input is inverted. factory default 00h read access pw2 or (pw1 and rwtbl2) or (pw1 and rtbl2) write access pw2 or (pw1 and rwtbl2) a2h and b2h memory common a2h and b2h memory locations memory type nonvolatile (see) 8bh reserved reserved reserved reserved 2 3 2 2 2 1 reserved bit 7 bit 0 this value becomes the i 2 c slave address for the main memory when the asel bit (table 02h, register 88h) is set. if a0h/b0h is programmed to this register, the auxiliary memory is disabled. for example, writing xxxx_010x makes the main device addresses a4h and b4h.
ds1877 sfp controller for dual rx interface 48 table 02h, register 8ch: reserved table 02h, register 8dh: force rssi factory default read access n/a write access n/a a2h and b2h memory n/a memory type n/a this register is reserved. factory default 00h read access pw2 or (pw1 and rwtbl2) or (pw1 and rtbl2) write access pw2 or (pw1 and rwtbl2) a2h and b2h memory common a2h and b2h memory locations memory type nonvolatile (see) 8dh reserved xoveren2 rssi2_fc rssi2_ff reserved xoveren1 rssi1_fc rssi1_ff bit 7 bit 0 bits 7, 3 reserved bit 6 xoveren2: enables rssi conversion to use the xover2 value during rssi2 conversions. 0 = uses hysteresis for linear rssi measurements. 1 = xover2 value is enabled for nonlinear rssi measurements. bits 5:4 rssi2_fc and rssi2_ff: rssi2 force coarse and rssi2 force fine. control bits for rssi mode of operation on the rssi2 conversion. 00b = (default) normal rssi mode of operation. 01b = the fine settings of scale and offset are used for rssi2 conversions. 10b = the coarse settings of scale and offset are used for rssi2 conversions. 11b = normal rssi mode of operation. bit 2 xoveren1: enables rssi conversion to use the xover1 value during rssi1 conversions. 0 = uses hysteresis for linear rssi measurements. 1 = xover1 value is enabled for nonlinear rssi measurements. bits 1:0 rssi1_fc and rssi1_ff: rssi1 force coarse and rssi1 force fine. control bits for rssi mode of operation on the rssi1 conversion. 00b = (default) normal rssi mode of operation. 01b = the fine settings of scale and offset are used for rssi1 conversions. 10b = the coarse settings of scale and offset are used for rssi1 conversions. 11b = normal rssi mode of operation.
ds1877 sfp controller for dual rx interface 49 table 02h, register 8eh: right-shift 2 (rshift 2 ) table 02h, register 8fh: right-shift 1 (rshift 1 ) table 02h, register 90h C 91h: reserved factory default 00h read access pw2 or (pw1 and rwtbl2) or (pw1 and rtbl2) write access pw2 or (pw1 and rwtbl2) a2h and b2h memory common a2h and b2h memory locations memory type nonvolatile (see) 8eh reserved rssi2c 2 rssi2c 1 rssi2c 0 reserved rssi2f 2 rssi2f 1 rssi2f 0 bit 7 bit 0 allows for right-shifting the final answer of rssi2 coarse and rssi2 fine. this allows for scaling the measurement to the smallest full-scale voltage and then right-shifting the final result so the reading is weighted to the correct lsb. factory default 00h read access pw2 or (pw1 and rwtbl2) or (pw1 and rtbl2) write access pw2 or (pw1 and rwtbl2) a2h and b2h memory common a2h and b2h memory locations memory type nonvolatile (see) 8fh reserved rssi1c 2 rssi1c 1 rssi1c 0 reserved rssi1f 2 rssi1f 1 rssi1f 0 bit 7 bit 0 allows for right-shifting the final answer of rssi1 coarse and rssi1 fine. this allows for scaling the measure - ments to the smallest full-scale voltage and then right-shifting the final result so the reading is weighted to the cor - rect lsb. factory default 00h read access n/a write access n/a a2h and b2h memory n/a memory type n/a these registers are reserved.
ds1877 sfp controller for dual rx interface 50 table 02h, register 92h C 93h: v cc scale table 02h, register 94h C 95h: xover2 coarse table 02h, register 96h C 97h: xover2 fine table 02h, register 98h C 99h: rssi2 coarse scale table 02h, register 9ah C 9bh: rssi2 fine scale table 02h, register 9ch C 9dh: rssi1 coarse scale table 02h, register 9eh C 9fh: rssi1 fine scale table 02h, register a0h C a1h: internal temp offset factory calibrated read access pw2 or (pw1 and rwtbl2) or (pw1 and rtbl2) write access pw2 or (pw1 and rwtbl2) a2h and b2h memory common a2h and b2h memory locations memory type nonvolatile (see) 92h, 94h, 96h, 98h, 9ah, 9ch, 9eh 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 93h, 95h, 97h, 99h, 9bh, 9dh, 9fh 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 controls the scaling or gain of the full-scale voltage measurements. the factory-calibrated value produces an fs voltage of 6.5536v for v cc , 2.5v for rssi2 coarse and rssi1 coarse, and 0.3125v for rssi2 fine and rssi1 fine. factory calibrated read access pw2 or (pw1 and rwtbl2) or (pw1 and rtbl2) write access pw2 or (pw1 and rwtbl2) a2h and b2h memory common a2h and b2h memory locations memory type nonvolatile (see) a0h s 2 8 2 7 2 6 2 5 2 4 2 3 2 2 a1h 2 1 2 0 2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 bit 7 bit 0 allows for offset control of temperature measurement if desired. the final result must be xored with bb40h before writing to this register. factory calibration contains the desired value for a reading in degrees celsius.
ds1877 sfp controller for dual rx interface 51 table 02h, register a2h C a3h: v cc offset table 02h, register a4h C a5h: xover1 coarse table 02h, register a6h C a7h: xover1 fine table 02h, register a8h C a9h: rssi2 coarse offset table 02h, register aah C abh: rssi2 fine offset table 02h, register ach C adh: rssi1 coarse offset table 02h, register aeh C afh: rssi1 fine offset factory default 00h read access pw2 or (pw1 and rwtbl2) or (pw1 and rtbl2) write access pw2 or (pw1 and rwtbl2) a2h and b2h memory common a2h and b2h memory locations memory type nonvolatile (see) a2h, a4h, a6h, a8h, aah, ach, aeh s s 2 15 2 14 2 13 2 12 2 11 2 10 a3h, a5h, a7h, a9h, abh, adh, afh 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 bit 7 bit 0 allows for offset control of these voltage measurements if desired. this number is twos complement.
ds1877 sfp controller for dual rx interface 52 table 02h, register b4h C b7h: pw2 table 02h, register b0h C b3h: pw1 factory default ffff ffffh read access n/a write access pw2 or (pw1 and wpw1) memory type nonvolatile (see) b0h 2 31 2 30 2 29 2 28 2 27 2 26 2 25 2 24 b1h 2 23 2 22 2 21 2 20 2 19 2 18 2 17 2 16 b2h 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 b3h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 the pwe value is compared against the value written to this location to enable pw1 access. at power-on, the pwe value is set to all ones. thus, writing these bytes to all ones grants pw1 access on power-on without writing the password entry. all reads of this register are 00h. factory default ffff ffffh read access n/a write access pw2 memory type nonvolatile (see) b4h 2 31 2 30 2 29 2 28 2 27 2 26 2 25 2 24 b5h 2 23 2 22 2 21 2 20 2 19 2 18 2 17 2 16 b6h 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 b7h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 the pwe value is compared against the value written to this location to enable pw2 access. at power-on, the pwe value is set to all ones. thus, writing these bytes to all ones grants pw2 access on power-on without writing the password entry. all reads of this register are 00h.
ds1877 sfp controller for dual rx interface 53 table 02h, register b8h: los ranging 2 factory default 00h read access pw2 or (pw1 and rwtbl2) or (pw1 and rtbl2) write access pw2 or (pw1 and rwtbl2) a2h and b2h memory common a2h and b2h memory location memory type nonvolatile (see) b8h reserved hlos2 2 hlos2 1 hlos2 0 reserved llos2 2 llos2 1 llos2 0 bit 7 bit 0 this register controls the full-scale range of the qt monitoring for the rssi2 differential inputs. bits 7, 3 reserved (default = 0) bits 6:4 hlos2[2:0]: hlos2 full-scale ranging: 3-bit value to select the full-scale comparison voltage for high los found on rssi2. default is 000b and creates a full scale of 1.25v. hlos2[2:0] % of 1.25v fs voltage (v) 000b 100.00 1.250 001b 80.02 1.0003 010b 66.69 0.8336 011b 50.05 0.6256 100b 40.05 0.5006 101b 33.38 0.4172 110b 28.62 0.3578 111b 25.04 0.313 bits 2:0 llos2[2:0]: llos2 full-scale ranging: 3-bit value to select the full-scale comparison voltage for low los found on rssi2. default is 000b and creates a full scale of 1.25v. llos2[2:0] % of 1.25v fs voltage (v) 000b 100.00 1.250 001b 80.02 1.0003 010b 66.69 0.8336 011b 50.05 0.6256 100b 40.05 0.5006 101b 33.38 0.4172 110b 28.62 0.3578 111b 25.04 0.313
ds1877 sfp controller for dual rx interface 54 table 02h, register b9h: reserved table 02h, register bah: hlos2 table 02h, register bbh: llos2 factory default 00h read access n/a write access n/a a2h and b2h memory n/a memory type n/a this register is reserved. factory default 00h read access pw2 or (pw1 and rwtbl2) or (pw1 and rtbl2) write access (pw2 and qt2en = 0) or (pw1 and rwtbl2 and qt2en = 0) a2h and b2h memory common a2h and b2h memory locations memory type nonvolatile (see) bah 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 fast comparison dac threshold adjust for high los2. the combination of hlos2 and llos2 creates a hys - teresis comparator. as rssi2 falls below the llos2 threshold, the los2 lo alarm bit is set to 1. the los2 lo alarm remains set until the rssi2 input is found above the hlos2 threshold setting, which clears the los2 lo alarm bit and sets the los2 hi alarm bit. factory default 00h read access pw2 or (pw1 and rwtbl2) or (pw1 and rtbl2) write access (pw2 and qt2en = 0) or (pw1 and rwtbl2 and qt2en = 0) a2h and b2h memory common a2h and b2h memory locations memory type nonvolatile (see) bbh 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 fast comparison dac threshold adjust for low los2. see hlos2 (table 02h, register bah) for the functional description.
ds1877 sfp controller for dual rx interface 55 table 02h, register bch: los ranging 1 factory default 00h read access pw2 or (pw1 and rwtbl2) or (pw1 and rtbl2) write access pw2 or (pw1 and rwtbl2) a2h and b2h memory common a2h and b2h memory locations memory type nonvolatile (see) bch reserved hlos1 2 hlos1 1 hlos1 0 reserved llos1 2 llos1 1 llos1 0 bit 7 bit 0 this register controls the full-scale range of the qt monitoring for the rssi1 differential inputs. bits 7, 3 reserved (default = 0) bits 6:4 hlos1[2:0]: hlos1 full-scale ranging: 3-bit value to select the full-scale comparison voltage for high los found on rssi1. default is 000b and creates a full scale of 1.25v. hlos1[2:0] % of 1.25v fs voltage (v) 000b 100.00 1.250 001b 80.02 1.0003 010b 66.69 0.8336 011b 50.05 0.6256 100b 40.05 0.5006 101b 33.38 0.4172 110b 28.62 0.3578 111b 25.04 0.313 bits 2:0 llos1[2:0]: llos1 full-scale ranging: 3-bit value to select the full-scale comparison voltage for low los found on rssi1. default is 000b and creates a full scale of 1.25v. llos1[2:0] % of 1.25v fs voltage (v) 000b 100.00 1.250 001b 80.02 1.0003 010b 66.69 0.8336 011b 50.05 0.6256 100b 40.05 0.5006 101b 33.38 0.4172 110b 28.62 0.3578 111b 25.04 0.313
ds1877 sfp controller for dual rx interface 56 table 02h, register beh: hlos1 table 02h, register bdh: reserved table 02h, register bfh: llos1 factory default 00h read access n/a write access n/a a2h and b2h memory n/a memory type n/a this register is reserved. factory default 00h read access pw2 or (pw1 and rwtbl2) or (pw1 and rtbl2) write access (pw2 and qt2en = 0) or (pw1 and rwtbl2 and qt2en = 0) a2h and b2h memory common a2h and b2h memory locations memory type nonvolatile (see) bfh 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 fast comparison dac threshold adjust for low los1. see hlos1 (table 02h, register beh) for the functional description. factory default 00h read access pw2 or (pw1 and rwtbl2) or (pw1 and rtbl2) write access (pw2 and qt2en = 0) or (pw1 and rwtbl2 and qt2en = 0) a2h and b2h memory common a2h and b2h memory locations memory type nonvolatile (see) beh 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 fast comparison dac threshold adjust for high los1. the combination of hlos1 and llos1 creates a hys - teresis comparator. as rssi1 falls below the llos1 threshold, the los1 lo alarm bit is set to 1. the los1 lo alarm remains set until the rssi1 input is found above the hlos1 threshold setting, which clears the los1 lo alarm bit and sets the los1 hi alarm bit.
ds1877 sfp controller for dual rx interface 57 table 02h, register c0h: pw_ena factory default 10h read access pw2 or (pw1 and rwtbl2) or (pw1 and rtbl2) write access pw2 or (pw1 and rwtbl2) a2h and b2h memory common a2h and b2h memory locations memory type nonvolatile (see) c0h reserved rwtbl1c rwtbl2 rwtbl1a rwtbl1b wlower wauxa wauxb bit 7 bit 0 bit 7 reserved bit 6 rwtbl1c: table 01h or 05h bytes f8hCffh. table address is dependent on mask bit (table 02h, register 88h). 0 = (default) read and write access for pw2 only. 1 = read and write access for both pw1 and pw2. bit 5 rwtbl2: table 02h. writing a nonvolatile value to this bit requires pw2 access. 0 = (default) read and write access for pw2 only. 1 = read and write access for both pw1 and pw2. bit 4 rwtbl1a: table 01h, registers 80hCbfh. 0 = read and write access for pw2 only. 1 = (default) read and write access for both pw1 and pw2. bit 3 rwtbl1b: table 01h, registers c0hCf7h. 0 = (default) read and write access for pw2 only. 1 = read and write access for both pw1 and pw2. bit 2 wlower: bytes 00hC5fh in main memory. all users can read this area. 0 = (default) write access for pw2 only. 1 = write access for both pw1 and pw2. bit 1 wauxa: auxiliary memory, registers 00hC7fh. all users can read this area. 0 = (default) write access for pw2 only. 1 = write access for both pw1 and pw2. bit 0 wauxb: auxiliary memory, registers 80hCffh. all users can read this area. 0 = (default) write access for pw2 only. 1 = write access for both pw1 and pw2.
ds1877 sfp controller for dual rx interface 58 table 02h, register c1h: pw_enb factory default 03h read access pw2 or (pw1 and rwtbl2) or (pw1 and rtbl2) write access pw2 or (pw1 and rwtbl2) a2h and b2h memory common a2h and b2h memory locations memory type nonvolatile (see) c1h rwtbl46 rtbl1c rtbl2 rtbl1a rtbl1b wpw1 wauxau wauxbu bit 7 bit 0 bit 7 rwtbl46: table 04h. 0 = (default) read and write access for pw2 only. 1 = read and write access for pw1 and pw2. bit 6 rtbl1c: table 01h or table 05h, registers f8hCffh. table address is dependent on mask bit (table 02h, register 88h). 0 = (default) read access for pw2 only. 1 = read access for pw1 and pw2. bit 5 rtbl2: table 02h. 0 = (default) read access for pw2 only. 1 = read access for pw1 and pw2. bit 4 rtbl1a: table 01h, registers 80hCbfh. 0 = (default) read access for pw2 only. 1 = read access for pw1 and pw2. bit 3 rtbl1b: table 01h, registers c0hCf7h. 0 = (default) read access for pw2 only. 1 = read access for pw1 and pw2. bit 2 wpw1: register pw1 (table 02h, registers b0hCb3h). 0 = (default) write access for pw2 only. 1 = write access for pw1 and pw2. bit 1 wauxau: auxiliary memory, registers 00hC7fh. all users can read this area. 0 = write access for pw2 only. 1 = (default) write access for user, pw1, and pw2. bit 0 wauxbu: auxiliary memory, registers 80hCffh. all users can read this area. 0 = write access for pw2 only. 1 = (default) write access for user, pw1, and pw2.
ds1877 sfp controller for dual rx interface 59 table 02h, register c6h: polarity table 02h, register c2h C c5h: reserved factory default 00h read access n/a write access n/a a2h and b2h memory n/a memory type n/a these registers are reserved. factory default 0ah read access pw2 or (pw1 and rwtbl2) or (pw1 and rtbl2) write access pw2 or (pw1 and rwtbl2) a2h and b2h memory common a2h and b2h memory locations memory type nonvolatile (see) c6h reserved reserved reserved reserved dac2p reserved dac1p reserved bit 7 bit 0 bits 7:4, 2, 0 reserved bit 3 dac2p: dac2 value polarity. the dac2 value (table 02h, registers c8hCc9h) range is 000hC3ffh. a setting of 000h creates a pulse-density of zero and 3ffh creates a pulse-density of 1023/1024. this polarity bit allows the user to use gnd or v refin as the reference. the power-on of dac2 value is 000h; thus an application that needs v refin to be the off state should use the inverted polarity. 0 = normal polarity. a setting of 000h results in a pulse-density output of zero held at gnd, and a setting of 3ffh results in a pulsed-density output of 1023/1024 held mostly at v refin . 1 = inverted polarity. a setting of 000h results in a pulse-density output of zero held at v refin, and a setting of 3ffh results in a pulsed-density output of 1023/1024 held mostly at gnd. bit 1 dac1p: dac1 value polarity. the dac1 value (table 02h, registers cchCcdh) range is 000hC3ffh. a setting of 000h creates a pulse-density of zero and 3ffh creates a pulse-density of 1023/1024. this polarity bit allows the user to use gnd or v refin as the reference. the power-on of dac1 value is 000h; thus an application that needs v refin to be the off state should use the inverted polarity. 0 = normal polarity. a setting of 000h results in a pulse-density output of zero held at gnd, and a setting of 3ffh results in a pulsed-density output of 1023/1024 held mostly at v refin . 1 = inverted polarity. a setting of 000h results in a pulse-density output of zero held at v refin, and a setting of 3ffh results in a pulsed-density output of 1023/1024 held mostly at gnd.
ds1877 sfp controller for dual rx interface 60 table 02h, register c7h: tblselpon table 02h, register c8h C c9h: dac2 value table 02h, register cah C cbh: reserved factory default 00h read access pw2 or (pw1 and rwtbl2) or (pw1 and rtbl2) write access pw2 or (pw1 and rwtbl2) a2h and b2h memory common a2h and b2h memory locations memory type nonvolatile (see) c7h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 chooses the initial value for the tbl sel byte (lower memory, register 7fh) at power-on. factory default 0000h read access pw2 or (pw1 and rwtbl2) or (pw1 and rtbl2) write access (pw2 and dac2en = 0) or (pw1 and rwtbl2 and dac2en = 0) a2h and b2h memory common a2h and b2h memory locations memory type volatile c8h 0 0 0 0 0 0 2 9 2 8 c9h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 the digital value used for dac2 value. it is the result of lut4 plus dac2 offset times 4 recalled from address b0h, table 04h (registers f8hCffh) at the adjusted memory address found in tindex. this register is updated at the end of the temperature conversion. dac2 value = lut4 + dac2 offset x 4 refin dac2 d v v dac2 value 1024 = (if polarity = 0) refin dac2 refin d v v v dac value 1024 = ? (if polarity = 1) factory default 00h read access n/a write access n/a a2h and b2h memory n/a memory type none these registers do not exist.
ds1877 sfp controller for dual rx interface 61 table 02h, register ceh C cfh: reserved table 02h, register cch C cdh: dac1 value table 02h, register d0h C ffh: empty factory default 0000h read access pw2 or (pw1 and rwtbl2) or (pw1 and rtbl2) write access (pw2 and dac1en = 0) or (pw1 and rwtbl2 and dac1en = 0) a2h and b2h memory common a2h and b2h memory locations memory type volatile cch 0 0 0 0 0 0 2 9 2 8 cdh 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 the digital value used for dac1 value. it is the result of lut4 plus dac1 offset times 4 recalled from address a0h, table 04h (registers f8hCffh) at the adjusted memory address found in tindex. this register is updated at the end of the temperature conversion. dac1 value = lut4 + dac1 offset x 4 refin dac1 d v v dac1 value 1024 = (if polarity = 0) refin dac1 refin d v v v dac1 value 1024 = ? (if polarity = 1) factory default 00h read access n/a write access n/a a2h and b2h memory n/a memory type n/a these registers do not exist. factory default 00h read access n/a write access n/a a2h and b2h memory n/a memory type none these registers do not exist.
ds1877 sfp controller for dual rx interface 62 table 04h register descriptions table 04h, register 80h C c7h: dac lut table 02h, register c8h C f7h: empty factory default 00h read access pw2 or (pw1 and rwtbl46) write access pw2 or (pw1 and rwtbl46) a2h and b2h memory different a2h and b2h memory locations memory type nonvolatile (ee) 80hCc7h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 digital value for the dac1 value (a2h address) and dac2 value (b2h address) outputs. the dac lut is a set of registers assigned to hold the temperature profile for the dac1 and dac2 values. the temperature mea - surement is used to index the lut (tindex, table 02h, register 81h) in 2 n c increments from -40 n c to +102 n c, starting at 80h. register 80h defines the -40 n c to -38 n c dac output, register 81h defines -38 n c to -36 n c dac output, and so on. values recalled from this eeprom memory table are written into the dac1 and dac2 value (table 02h, registers c8hCc9h, cchCcdh) locations that hold the values until the next temperature conversion. the device can be placed into a manual mode (dac1en and dac2en bits, table 02h, register 80h), where dac1 and dac2 values are directly controlled for calibration. if the temperature compensation functionality is not required, program the entire table to the desired modulation setting. factory default 00h read access n/a write access n/a a2h and b2h memory n/a memory type none these registers do not exist.
ds1877 sfp controller for dual rx interface 63 table 04h, register f8h C ffh: dac offset lut auxiliary memory a0h register descriptions auxiliary memory a0h, register 00h C 7fh: eeprom factory default 00h read access pw2 or (pw1 and rwtbl46) write access pw2 or (pw1 and rwtbl46) a2h and b2h memory different a2h and b2h memory locations memory type nonvolatile (ee) f8hCffh 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 bit 7 bit 0 the digital value for the temperature offset of the dac1 and dac2 value outputs. f8h less than or equal to -8 n c f9h greater than -8 n c up to +8 n c fah greater than +8 n c up to +24 n c fbh greater than +24 n c up to +40 n c fch greater than +40 n c up to +56 n c fdh greater than +56 n c up to +72 n c feh greater than +72 n c up to +88 n c ffh greater than +88 n c the dac value is a 10-bit value. the dac lut is an 8-bit lut. the dac offset lut times 4 plus the dac lut makes use of the entire 10-bit range. factory default 00h read access all write access pw2 or (pw1 and wauxa) or wauxau memory type nonvolatile (ee) 00hC7fh 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 accessible with the slave address a0h.
ds1877 sfp controller for dual rx interface 64 auxiliary memory a0h, register 80h C ffh: eeprom applications information power-supply decoupling to achieve best results, it is recommended that the power supply is decoupled with a 0.01 f f or a 0.1 f f capacitor. use high-quality, ceramic, surface-mount capacitors, and mount the capacitors as close as possible to the v cc and gnd pins to minimize lead inductance. sda and scl pullup resistors sda is an open-collector output on the device that requires a pullup resistor to realize high logic levels. a master using either an open-collector output with a pul - lup resistor or a push-pull output driver can be used for scl. pullup resistor values should be chosen to ensure that the rise and fall times listed in the i 2 c ac electrical characteristics table are within specification. package information for the latest package outline information and land patterns, go to www.maxim-ic.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. factory default 00h read access all write access pw2 or (pw1 and wauxb) or wauxbu memory type nonvolatile (ee) 80hCffh 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 accessible with the slave address a0h. package type package code document no. 28 tqfn-ep t2855+6 21-0140
maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 65 ? 2010 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. ds1877 sfp controller for dual rx interface revision history revision number revision date description pages changed 0 3/10 initial release 1 4/10 updated figure 11 labels for los1/2 and invlosout, and corrected errors in the cnfgc, hlos2, and hlos1 bit tables. 19, 47, 54, 56

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